From: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
To: Tony Nguyen <anthony.l.nguyen@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Simon Horman <horms@kernel.org>,
Russell King <linux@armlinux.org.uk>,
Alexei Starovoitov <ast@kernel.org>,
Daniel Borkmann <daniel@iogearbox.net>,
Jesper Dangaard Brouer <hawk@kernel.org>,
John Fastabend <john.fastabend@gmail.com>,
Russell King <rmk+kernel@armlinux.org.uk>,
Furong Xu <0x1207@gmail.com>,
Vladimir Oltean <vladimir.oltean@nxp.com>,
Serge Semin <fancer.lancer@gmail.com>,
Xiaolei Wang <xiaolei.wang@windriver.com>,
Suraj Jaiswal <quic_jsuraj@quicinc.com>,
Kory Maincent <kory.maincent@bootlin.com>,
Petr Tesarik <petr@tesarici.cz>,
Faizal Rahim <faizal.abdul.rahim@linux.intel.com>,
Choong Yong Liang <yong.liang.choong@linux.intel.com>,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
Vinicius Costa Gomes <vinicius.gomes@intel.com>,
intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, bpf@vger.kernel.org
Subject: [PATCH iwl-next v2 7/9] igc: Add support for preemptible traffic class in taprio
Date: Wed, 5 Feb 2025 05:05:22 -0500 [thread overview]
Message-ID: <20250205100524.1138523-8-faizal.abdul.rahim@linux.intel.com> (raw)
In-Reply-To: <20250205100524.1138523-1-faizal.abdul.rahim@linux.intel.com>
Set queue as preemptible or express for taprio.
This will eventually set queue-specific preemptible field in TXQCTL
register.
Verified that the correct preemptible hardware queue is set using the
following commands:
a) 1:1 TC-to-Queue Mapping
$ sudo tc qdisc replace dev enp1s0 parent root handle 100 \
taprio num_tc 4 map 3 2 1 0 3 3 3 3 3 3 3 3 3 3 3 3 \
queues 1@0 1@1 1@2 1@3 base-time 0 sched-entry S F 100000 \
fp E E P P
b) Non-1:1 TC-to-Queue Mapping
$ sudo tc qdisc replace dev enp1s0 parent root handle 100 \
taprio num_tc 3 map 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 2
queues 2@0 1@2 1@3
fp E E P
Co-developed-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Signed-off-by: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
---
drivers/net/ethernet/intel/igc/igc.h | 2 +-
drivers/net/ethernet/intel/igc/igc_defines.h | 1 +
drivers/net/ethernet/intel/igc/igc_main.c | 36 ++++++++++++++++++++
drivers/net/ethernet/intel/igc/igc_tsn.c | 4 +++
4 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h
index 2f3662143589..e9f7a75aef13 100644
--- a/drivers/net/ethernet/intel/igc/igc.h
+++ b/drivers/net/ethernet/intel/igc/igc.h
@@ -163,7 +163,7 @@ struct igc_ring {
bool launchtime_enable; /* true if LaunchTime is enabled */
ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
ktime_t last_ff_cycle; /* Last cycle with an active first flag */
-
+ bool preemptible; /* True if not express */
u32 start_time;
u32 end_time;
u32 max_sdu;
diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h
index 9d7d903545ed..d7b4f5b6e548 100644
--- a/drivers/net/ethernet/intel/igc/igc_defines.h
+++ b/drivers/net/ethernet/intel/igc/igc_defines.h
@@ -559,6 +559,7 @@
#define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001
#define IGC_TXQCTL_STRICT_CYCLE 0x00000002
#define IGC_TXQCTL_STRICT_END 0x00000004
+#define IGC_TXQCTL_PREEMPTIBLE 0x00000008
#define IGC_TXQCTL_QAV_SEL_MASK 0x000000C0
#define IGC_TXQCTL_QAV_SEL_CBS0 0x00000080
#define IGC_TXQCTL_QAV_SEL_CBS1 0x000000C0
diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c
index 396410522e01..6f7f4c641393 100644
--- a/drivers/net/ethernet/intel/igc/igc_main.c
+++ b/drivers/net/ethernet/intel/igc/igc_main.c
@@ -6254,6 +6254,39 @@ static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now)
return timespec64_compare(now, &b) > 0;
}
+static u32 igc_map_tc_to_queue(const struct igc_adapter *adapter,
+ unsigned long preemptible_tcs)
+{
+ struct net_device *dev = adapter->netdev;
+ u32 i, queue = 0;
+
+ for (i = 0; i < dev->num_tc; i++) {
+ u32 offset, count;
+
+ if (!(preemptible_tcs & BIT(i)))
+ continue;
+
+ offset = dev->tc_to_txq[i].offset;
+ count = dev->tc_to_txq[i].count;
+ queue |= GENMASK(offset + count - 1, offset);
+ }
+
+ return queue;
+}
+
+static void igc_save_preempt_queue(struct igc_adapter *adapter,
+ const struct tc_mqprio_qopt_offload *mqprio)
+{
+ u32 preemptible_queue = igc_map_tc_to_queue(adapter,
+ mqprio->preemptible_tcs);
+
+ for (int i = 0; i < adapter->num_tx_queues; i++) {
+ struct igc_ring *tx_ring = adapter->tx_ring[i];
+
+ tx_ring->preemptible = preemptible_queue & BIT(i);
+ }
+}
+
static bool validate_schedule(struct igc_adapter *adapter,
const struct tc_taprio_qopt_offload *qopt)
{
@@ -6340,6 +6373,7 @@ static int igc_qbv_clear_schedule(struct igc_adapter *adapter)
ring->start_time = 0;
ring->end_time = NSEC_PER_SEC;
ring->max_sdu = 0;
+ ring->preemptible = false;
}
spin_lock_irqsave(&adapter->qbv_tx_lock, flags);
@@ -6496,6 +6530,8 @@ static int igc_save_qbv_schedule(struct igc_adapter *adapter,
ring->max_sdu = 0;
}
+ igc_save_preempt_queue(adapter, &qopt->mqprio);
+
return 0;
}
diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/ethernet/intel/igc/igc_tsn.c
index 50c343c59e29..61ad464ed053 100644
--- a/drivers/net/ethernet/intel/igc/igc_tsn.c
+++ b/drivers/net/ethernet/intel/igc/igc_tsn.c
@@ -459,6 +459,10 @@ static int igc_tsn_enable_offload(struct igc_adapter *adapter)
if (ring->launchtime_enable)
txqctl |= IGC_TXQCTL_QUEUE_MODE_LAUNCHT;
+ if (ethtool_mmsv_is_tx_active(&adapter->fpe.mmsv) &&
+ ring->preemptible)
+ txqctl |= IGC_TXQCTL_PREEMPTIBLE;
+
/* Skip configuring CBS for Q2 and Q3 */
if (i > 1)
goto skip_cbs;
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
To: Tony Nguyen <anthony.l.nguyen@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Simon Horman <horms@kernel.org>,
Russell King <linux@armlinux.org.uk>,
Alexei Starovoitov <ast@kernel.org>,
Daniel Borkmann <daniel@iogearbox.net>,
Jesper Dangaard Brouer <hawk@kernel.org>,
John Fastabend <john.fastabend@gmail.com>,
Russell King <rmk+kernel@armlinux.org.uk>,
Furong Xu <0x1207@gmail.com>,
Vladimir Oltean <vladimir.oltean@nxp.com>,
Serge Semin <fancer.lancer@gmail.com>,
Xiaolei Wang <xiaolei.wang@windriver.com>,
Suraj Jaiswal <quic_jsuraj@quicinc.com>,
Kory Maincent <kory.maincent@bootlin.com>,
Petr Tesarik <petr@tesarici.cz>,
Faizal Rahim <faizal.abdul.rahim@linux.intel.com>,
Choong Yong Liang <yong.liang.choong@linux.intel.com>,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
Vinicius Costa Gomes <vinicius.gomes@intel.com>,
intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, bpf@vger.kernel.org
Subject: [Intel-wired-lan] [PATCH iwl-next v2 7/9] igc: Add support for preemptible traffic class in taprio
Date: Wed, 5 Feb 2025 05:05:22 -0500 [thread overview]
Message-ID: <20250205100524.1138523-8-faizal.abdul.rahim@linux.intel.com> (raw)
In-Reply-To: <20250205100524.1138523-1-faizal.abdul.rahim@linux.intel.com>
Set queue as preemptible or express for taprio.
This will eventually set queue-specific preemptible field in TXQCTL
register.
Verified that the correct preemptible hardware queue is set using the
following commands:
a) 1:1 TC-to-Queue Mapping
$ sudo tc qdisc replace dev enp1s0 parent root handle 100 \
taprio num_tc 4 map 3 2 1 0 3 3 3 3 3 3 3 3 3 3 3 3 \
queues 1@0 1@1 1@2 1@3 base-time 0 sched-entry S F 100000 \
fp E E P P
b) Non-1:1 TC-to-Queue Mapping
$ sudo tc qdisc replace dev enp1s0 parent root handle 100 \
taprio num_tc 3 map 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 2
queues 2@0 1@2 1@3
fp E E P
Co-developed-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Signed-off-by: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
---
drivers/net/ethernet/intel/igc/igc.h | 2 +-
drivers/net/ethernet/intel/igc/igc_defines.h | 1 +
drivers/net/ethernet/intel/igc/igc_main.c | 36 ++++++++++++++++++++
drivers/net/ethernet/intel/igc/igc_tsn.c | 4 +++
4 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h
index 2f3662143589..e9f7a75aef13 100644
--- a/drivers/net/ethernet/intel/igc/igc.h
+++ b/drivers/net/ethernet/intel/igc/igc.h
@@ -163,7 +163,7 @@ struct igc_ring {
bool launchtime_enable; /* true if LaunchTime is enabled */
ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
ktime_t last_ff_cycle; /* Last cycle with an active first flag */
-
+ bool preemptible; /* True if not express */
u32 start_time;
u32 end_time;
u32 max_sdu;
diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h
index 9d7d903545ed..d7b4f5b6e548 100644
--- a/drivers/net/ethernet/intel/igc/igc_defines.h
+++ b/drivers/net/ethernet/intel/igc/igc_defines.h
@@ -559,6 +559,7 @@
#define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001
#define IGC_TXQCTL_STRICT_CYCLE 0x00000002
#define IGC_TXQCTL_STRICT_END 0x00000004
+#define IGC_TXQCTL_PREEMPTIBLE 0x00000008
#define IGC_TXQCTL_QAV_SEL_MASK 0x000000C0
#define IGC_TXQCTL_QAV_SEL_CBS0 0x00000080
#define IGC_TXQCTL_QAV_SEL_CBS1 0x000000C0
diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c
index 396410522e01..6f7f4c641393 100644
--- a/drivers/net/ethernet/intel/igc/igc_main.c
+++ b/drivers/net/ethernet/intel/igc/igc_main.c
@@ -6254,6 +6254,39 @@ static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now)
return timespec64_compare(now, &b) > 0;
}
+static u32 igc_map_tc_to_queue(const struct igc_adapter *adapter,
+ unsigned long preemptible_tcs)
+{
+ struct net_device *dev = adapter->netdev;
+ u32 i, queue = 0;
+
+ for (i = 0; i < dev->num_tc; i++) {
+ u32 offset, count;
+
+ if (!(preemptible_tcs & BIT(i)))
+ continue;
+
+ offset = dev->tc_to_txq[i].offset;
+ count = dev->tc_to_txq[i].count;
+ queue |= GENMASK(offset + count - 1, offset);
+ }
+
+ return queue;
+}
+
+static void igc_save_preempt_queue(struct igc_adapter *adapter,
+ const struct tc_mqprio_qopt_offload *mqprio)
+{
+ u32 preemptible_queue = igc_map_tc_to_queue(adapter,
+ mqprio->preemptible_tcs);
+
+ for (int i = 0; i < adapter->num_tx_queues; i++) {
+ struct igc_ring *tx_ring = adapter->tx_ring[i];
+
+ tx_ring->preemptible = preemptible_queue & BIT(i);
+ }
+}
+
static bool validate_schedule(struct igc_adapter *adapter,
const struct tc_taprio_qopt_offload *qopt)
{
@@ -6340,6 +6373,7 @@ static int igc_qbv_clear_schedule(struct igc_adapter *adapter)
ring->start_time = 0;
ring->end_time = NSEC_PER_SEC;
ring->max_sdu = 0;
+ ring->preemptible = false;
}
spin_lock_irqsave(&adapter->qbv_tx_lock, flags);
@@ -6496,6 +6530,8 @@ static int igc_save_qbv_schedule(struct igc_adapter *adapter,
ring->max_sdu = 0;
}
+ igc_save_preempt_queue(adapter, &qopt->mqprio);
+
return 0;
}
diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/ethernet/intel/igc/igc_tsn.c
index 50c343c59e29..61ad464ed053 100644
--- a/drivers/net/ethernet/intel/igc/igc_tsn.c
+++ b/drivers/net/ethernet/intel/igc/igc_tsn.c
@@ -459,6 +459,10 @@ static int igc_tsn_enable_offload(struct igc_adapter *adapter)
if (ring->launchtime_enable)
txqctl |= IGC_TXQCTL_QUEUE_MODE_LAUNCHT;
+ if (ethtool_mmsv_is_tx_active(&adapter->fpe.mmsv) &&
+ ring->preemptible)
+ txqctl |= IGC_TXQCTL_PREEMPTIBLE;
+
/* Skip configuring CBS for Q2 and Q3 */
if (i > 1)
goto skip_cbs;
--
2.34.1
next prev parent reply other threads:[~2025-02-05 10:06 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-05 10:05 [PATCH iwl-next v2 0/9] igc: Add support for Frame Preemption feature in IGC Faizal Rahim
2025-02-05 10:05 ` [Intel-wired-lan] " Faizal Rahim
2025-02-05 10:05 ` [PATCH iwl-next v2 1/9] net: ethtool: mm: extract stmmac verification logic into common library Faizal Rahim
2025-02-05 10:05 ` [Intel-wired-lan] " Faizal Rahim
2025-02-05 10:05 ` [PATCH iwl-next v2 2/9] igc: Rename xdp_get_tx_ring() for non-xdp usage Faizal Rahim
2025-02-05 10:05 ` [Intel-wired-lan] " Faizal Rahim
2025-02-05 10:05 ` [PATCH iwl-next v2 3/9] igc: Optimize the TX packet buffer utilization Faizal Rahim
2025-02-05 10:05 ` [Intel-wired-lan] " Faizal Rahim
2025-02-05 10:05 ` [PATCH iwl-next v2 4/9] igc: Set the RX packet buffer size for TSN mode Faizal Rahim
2025-02-05 10:05 ` [Intel-wired-lan] " Faizal Rahim
2025-02-05 10:05 ` [PATCH iwl-next v2 5/9] igc: Add support for frame preemption verification Faizal Rahim
2025-02-05 10:05 ` [Intel-wired-lan] " Faizal Rahim
2025-02-05 17:12 ` Vladimir Oltean
2025-02-05 17:12 ` [Intel-wired-lan] " Vladimir Oltean
2025-02-06 14:40 ` Abdul Rahim, Faizal
2025-02-06 14:40 ` [Intel-wired-lan] " Abdul Rahim, Faizal
2025-02-06 15:04 ` Vladimir Oltean
2025-02-06 15:04 ` [Intel-wired-lan] " Vladimir Oltean
2025-02-07 16:59 ` Abdul Rahim, Faizal
2025-02-07 16:59 ` [Intel-wired-lan] " Abdul Rahim, Faizal
2025-02-05 10:05 ` [PATCH iwl-next v2 6/9] igc: Add support to set tx-min-frag-size Faizal Rahim
2025-02-05 10:05 ` [Intel-wired-lan] " Faizal Rahim
2025-02-05 10:05 ` Faizal Rahim [this message]
2025-02-05 10:05 ` [Intel-wired-lan] [PATCH iwl-next v2 7/9] igc: Add support for preemptible traffic class in taprio Faizal Rahim
2025-02-05 10:05 ` [PATCH iwl-next v2 8/9] igc: Add support to get MAC Merge data via ethtool Faizal Rahim
2025-02-05 10:05 ` [Intel-wired-lan] " Faizal Rahim
2025-02-05 10:05 ` [PATCH iwl-next v2 9/9] igc: Add support to get frame preemption statistics " Faizal Rahim
2025-02-05 10:05 ` [Intel-wired-lan] " Faizal Rahim
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250205100524.1138523-8-faizal.abdul.rahim@linux.intel.com \
--to=faizal.abdul.rahim@linux.intel.com \
--cc=0x1207@gmail.com \
--cc=alexandre.torgue@foss.st.com \
--cc=andrew+netdev@lunn.ch \
--cc=anthony.l.nguyen@intel.com \
--cc=ast@kernel.org \
--cc=bpf@vger.kernel.org \
--cc=daniel@iogearbox.net \
--cc=davem@davemloft.net \
--cc=edumazet@google.com \
--cc=fancer.lancer@gmail.com \
--cc=hawk@kernel.org \
--cc=hayashi.kunihiko@socionext.com \
--cc=horms@kernel.org \
--cc=intel-wired-lan@lists.osuosl.org \
--cc=john.fastabend@gmail.com \
--cc=kory.maincent@bootlin.com \
--cc=kuba@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-stm32@st-md-mailman.stormreply.com \
--cc=linux@armlinux.org.uk \
--cc=mcoquelin.stm32@gmail.com \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=petr@tesarici.cz \
--cc=przemyslaw.kitszel@intel.com \
--cc=quic_jsuraj@quicinc.com \
--cc=rmk+kernel@armlinux.org.uk \
--cc=vinicius.gomes@intel.com \
--cc=vladimir.oltean@nxp.com \
--cc=xiaolei.wang@windriver.com \
--cc=yong.liang.choong@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.