From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
qemu-riscv@nongnu.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Bin Meng" <bmeng.cn@gmail.com>,
"Weiwei Li" <liwei1518@gmail.com>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 7/7] hw/riscv: Move few objects to common_ss[] to build them once
Date: Thu, 6 Feb 2025 19:18:27 +0100 [thread overview]
Message-ID: <20250206181827.41557-8-philmd@linaro.org> (raw)
In-Reply-To: <20250206181827.41557-1-philmd@linaro.org>
opentitan.c, riscv-iommu-pci.c, riscv-iommu-sys.c don't depend
on target-specific knowledge. Move them to common_ss[] to build
them once.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/riscv/meson.build | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 3c7e083aca1..ff578a2e01a 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -2,7 +2,7 @@ riscv_ss = ss.source_set()
riscv_ss.add(files('boot.c'))
riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
riscv_ss.add(files('riscv_hart.c'))
-riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
+common_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
@@ -10,7 +10,8 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
-riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c'))
+riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c'))
+common_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu-pci.c', 'riscv-iommu-sys.c'))
riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))
hw_arch += {'riscv': riscv_ss}
--
2.47.1
prev parent reply other threads:[~2025-02-06 18:20 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 18:18 [PATCH 0/7] hw/riscv: Move few units to common_ss[] Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 1/7] MAINTAINERS: Unify Alistair's professional email address Philippe Mathieu-Daudé
2025-02-06 18:19 ` Philippe Mathieu-Daudé
2025-02-06 20:54 ` Richard Henderson
2025-02-10 0:24 ` Alistair Francis
2025-02-06 18:18 ` [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h' Philippe Mathieu-Daudé
2025-02-08 16:51 ` Philippe Mathieu-Daudé
2025-02-09 7:34 ` Paolo Bonzini
2025-03-06 7:47 ` Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 3/7] hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header Philippe Mathieu-Daudé
2025-02-06 20:54 ` Richard Henderson
2025-02-10 0:21 ` Alistair Francis
2025-02-06 18:18 ` [PATCH 4/7] hw/riscv/boot: Use 'hwaddr' type for firmware addresses Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 5/7] hw/riscv/iommu: Reduce needs for target-specific code Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 6/7] hw/riscv/hart: Make 'riscv_hart.h' header target-agnostic Philippe Mathieu-Daudé
2025-02-06 18:18 ` Philippe Mathieu-Daudé [this message]
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