From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h'
Date: Thu, 6 Mar 2025 08:47:38 +0100 [thread overview]
Message-ID: <34ea7324-2df6-4c97-97d3-b37463a3ff7b@linaro.org> (raw)
In-Reply-To: <1faf3550-909d-47ba-89e5-c8955a03784e@redhat.com>
On 9/2/25 08:34, Paolo Bonzini wrote:
> On 2/6/25 19:18, Philippe Mathieu-Daudé wrote:
>> "cpu.h" is target-specific. Definitions which can be used
>> by hw/ code when building QOM blocks can be in "cpu-qom.h",
>> which is target-agnostic.
>>
>> Move the MISA bits (removing the pointless target_ulong cast)
>> and the IRQ index definitions.
>
> This seems wrong. Why not move from cpu.h to cpu_bits.h, and include that?
Because of ...
>
> Paolo
>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> target/riscv/cpu-qom.h | 40 ++++++++++++++++++++++++++++++++++++++++
>> target/riscv/cpu.h | 24 ------------------------
>> target/riscv/cpu_bits.h | 15 ---------------
>> 3 files changed, 40 insertions(+), 39 deletions(-)
>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index f97c48a3943..80701bc77fe 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -720,21 +720,6 @@ typedef enum RISCVException {
>> #define RISCV_EXCP_INT_FLAG 0x80000000
>> #define RISCV_EXCP_INT_MASK 0x7fffffff
>> -/* Interrupt causes */
>> -#define IRQ_U_SOFT 0
>> -#define IRQ_S_SOFT 1
>> -#define IRQ_VS_SOFT 2
>> -#define IRQ_M_SOFT 3
>> -#define IRQ_U_TIMER 4
>> -#define IRQ_S_TIMER 5
>> -#define IRQ_VS_TIMER 6
>> -#define IRQ_M_TIMER 7
>> -#define IRQ_U_EXT 8
>> -#define IRQ_S_EXT 9
>> -#define IRQ_VS_EXT 10
>> -#define IRQ_M_EXT 11
>> -#define IRQ_S_GEXT 12
>> -#define IRQ_PMU_OVF 13
>> #define IRQ_LOCAL_MAX 64
>> /* -1 is due to bit zero of hgeip and hgeie being ROZ. */
>> #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1)
... this TARGET_LONG_BITS use in cpu_bits.h.
and:
target/riscv/cpu_bits.h:1070:44: error: attempt to use a poisoned identifier
1070 | #define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0
| ^
But I got your idea and will only move these 2 to "cpu.h".
next prev parent reply other threads:[~2025-03-06 7:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 18:18 [PATCH 0/7] hw/riscv: Move few units to common_ss[] Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 1/7] MAINTAINERS: Unify Alistair's professional email address Philippe Mathieu-Daudé
2025-02-06 18:19 ` Philippe Mathieu-Daudé
2025-02-06 20:54 ` Richard Henderson
2025-02-10 0:24 ` Alistair Francis
2025-02-06 18:18 ` [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h' Philippe Mathieu-Daudé
2025-02-08 16:51 ` Philippe Mathieu-Daudé
2025-02-09 7:34 ` Paolo Bonzini
2025-03-06 7:47 ` Philippe Mathieu-Daudé [this message]
2025-02-06 18:18 ` [PATCH 3/7] hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header Philippe Mathieu-Daudé
2025-02-06 20:54 ` Richard Henderson
2025-02-10 0:21 ` Alistair Francis
2025-02-06 18:18 ` [PATCH 4/7] hw/riscv/boot: Use 'hwaddr' type for firmware addresses Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 5/7] hw/riscv/iommu: Reduce needs for target-specific code Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 6/7] hw/riscv/hart: Make 'riscv_hart.h' header target-agnostic Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 7/7] hw/riscv: Move few objects to common_ss[] to build them once Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=34ea7324-2df6-4c97-97d3-b37463a3ff7b@linaro.org \
--to=philmd@linaro.org \
--cc=alistair.francis@wdc.com \
--cc=bmeng.cn@gmail.com \
--cc=dbarboza@ventanamicro.com \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=sunilvl@ventanamicro.com \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.