From: Alexander Sverdlin <alexander.sverdlin@gmail.com>
To: soc@lists.linux.dev
Cc: Alexander Sverdlin <alexander.sverdlin@gmail.com>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@outlook.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Haylen Chu <heylenay@outlook.com>,
linux-arm-kernel@lists.infradead.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Arnd Bergmann <arnd@arndb.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Subject: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts
Date: Sun, 9 Feb 2025 23:06:27 +0100 [thread overview]
Message-ID: <20250209220646.1090868-3-alexander.sverdlin@gmail.com> (raw)
In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com>
Make the peripheral device tree re-usable on ARM64 platform by splitting it
into CPU-core specific and peripheral parts.
Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
into "plic" interrupt-controller numbering.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 313 ++++++++++++++++++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 305 +----------------
3 files changed, 317 insertions(+), 303 deletions(-)
create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
index 5fd14dd1b14f..bbdb30653e9a 100644
--- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
@@ -11,7 +11,7 @@ soc {
emmc: mmc@4300000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4300000 0x1000>;
- interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_EMMC>,
<&clk CLK_EMMC>;
clock-names = "core", "bus";
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
new file mode 100644
index 000000000000..53834b0658b2
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dt-bindings/clock/sophgo,cv1800.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_25m";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk: clock-controller@3002000 {
+ reg = <0x03002000 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ gpio0: gpio@3020000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio1: gpio@3021000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3021000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio2: gpio@3022000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3022000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portc: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio3: gpio@3023000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3023000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portd: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ saradc: adc@30f0000 {
+ compatible = "sophgo,cv1800b-saradc";
+ reg = <0x030f0000 0x1000>;
+ clocks = <&clk CLK_SARADC>;
+ interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ channel@0 {
+ reg = <0>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ };
+ };
+
+ i2c0: i2c@4000000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x04000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
+ clock-names = "ref", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@4010000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x04010000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
+ clock-names = "ref", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@4020000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x04020000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
+ clock-names = "ref", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@4030000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x04030000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
+ clock-names = "ref", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@4040000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x04040000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
+ clock-names = "ref", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart0: serial@4140000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04140000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@4150000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04150000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@4160000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04160000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@4170000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04170000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi0: spi@4180000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x04180000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
+ clock-names = "ssi_clk", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi1: spi@4190000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x04190000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
+ clock-names = "ssi_clk", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi2: spi@41a0000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x041a0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
+ clock-names = "ssi_clk", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi3: spi@41b0000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x041b0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
+ clock-names = "ssi_clk", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart4: serial@41c0000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x041c0000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ sdhci0: mmc@4310000 {
+ compatible = "sophgo,cv1800b-dwcmshc";
+ reg = <0x4310000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_AXI4_SD0>,
+ <&clk CLK_SD0>;
+ clock-names = "core", "bus";
+ status = "disabled";
+ };
+
+ sdhci1: mmc@4320000 {
+ compatible = "sophgo,cv1800b-dwcmshc";
+ reg = <0x4320000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_AXI4_SD1>,
+ <&clk CLK_SD1>;
+ clock-names = "core", "bus";
+ status = "disabled";
+ };
+
+ dmac: dma-controller@4330000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x04330000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
+ clock-names = "core-clk", "cfgr-clk";
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ snps,block-size = <1024 1024 1024 1024
+ 1024 1024 1024 1024>;
+ snps,priority = <0 1 2 3 4 5 6 7>;
+ snps,dma-masters = <2>;
+ snps,data-width = <4>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index c18822ec849f..57a01b71aa67 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -4,9 +4,9 @@
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
-#include <dt-bindings/clock/sophgo,cv1800.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
+
+#include "cv18xx-periph.dtsi"
/ {
#address-cells = <1>;
@@ -41,310 +41,11 @@ cpu0_intc: interrupt-controller {
};
};
- osc: oscillator {
- compatible = "fixed-clock";
- clock-output-names = "osc_25m";
- #clock-cells = <0>;
- };
-
soc {
- compatible = "simple-bus";
interrupt-parent = <&plic>;
- #address-cells = <1>;
- #size-cells = <1>;
dma-noncoherent;
ranges;
- clk: clock-controller@3002000 {
- reg = <0x03002000 0x1000>;
- clocks = <&osc>;
- #clock-cells = <1>;
- };
-
- gpio0: gpio@3020000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0x3020000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- porta: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- gpio1: gpio@3021000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0x3021000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- portb: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- gpio2: gpio@3022000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0x3022000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- portc: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- gpio3: gpio@3023000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0x3023000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- portd: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- saradc: adc@30f0000 {
- compatible = "sophgo,cv1800b-saradc";
- reg = <0x030f0000 0x1000>;
- clocks = <&clk CLK_SARADC>;
- interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- channel@0 {
- reg = <0>;
- };
-
- channel@1 {
- reg = <1>;
- };
-
- channel@2 {
- reg = <2>;
- };
- };
-
- i2c0: i2c@4000000 {
- compatible = "snps,designware-i2c";
- reg = <0x04000000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
- clock-names = "ref", "pclk";
- interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- i2c1: i2c@4010000 {
- compatible = "snps,designware-i2c";
- reg = <0x04010000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
- clock-names = "ref", "pclk";
- interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- i2c2: i2c@4020000 {
- compatible = "snps,designware-i2c";
- reg = <0x04020000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
- clock-names = "ref", "pclk";
- interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- i2c3: i2c@4030000 {
- compatible = "snps,designware-i2c";
- reg = <0x04030000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
- clock-names = "ref", "pclk";
- interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- i2c4: i2c@4040000 {
- compatible = "snps,designware-i2c";
- reg = <0x04040000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
- clock-names = "ref", "pclk";
- interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- uart0: serial@4140000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04140000 0x100>;
- interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart1: serial@4150000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04150000 0x100>;
- interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart2: serial@4160000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04160000 0x100>;
- interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart3: serial@4170000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04170000 0x100>;
- interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- spi0: spi@4180000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0x04180000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
- clock-names = "ssi_clk", "pclk";
- interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- spi1: spi@4190000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0x04190000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
- clock-names = "ssi_clk", "pclk";
- interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- spi2: spi@41a0000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0x041a0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
- clock-names = "ssi_clk", "pclk";
- interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- spi3: spi@41b0000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0x041b0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
- clock-names = "ssi_clk", "pclk";
- interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- uart4: serial@41c0000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x041c0000 0x100>;
- interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- sdhci0: mmc@4310000 {
- compatible = "sophgo,cv1800b-dwcmshc";
- reg = <0x4310000 0x1000>;
- interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_AXI4_SD0>,
- <&clk CLK_SD0>;
- clock-names = "core", "bus";
- status = "disabled";
- };
-
- sdhci1: mmc@4320000 {
- compatible = "sophgo,cv1800b-dwcmshc";
- reg = <0x4320000 0x1000>;
- interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_AXI4_SD1>,
- <&clk CLK_SD1>;
- clock-names = "core", "bus";
- status = "disabled";
- };
-
- dmac: dma-controller@4330000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x04330000 0x1000>;
- interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
- clock-names = "core-clk", "cfgr-clk";
- #dma-cells = <1>;
- dma-channels = <8>;
- snps,block-size = <1024 1024 1024 1024
- 1024 1024 1024 1024>;
- snps,priority = <0 1 2 3 4 5 6 7>;
- snps,dma-masters = <2>;
- snps,data-width = <4>;
- status = "disabled";
- };
-
plic: interrupt-controller@70000000 {
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
--
2.48.1
WARNING: multiple messages have this Message-ID (diff)
From: Alexander Sverdlin <alexander.sverdlin@gmail.com>
To: soc@lists.linux.dev
Cc: Alexander Sverdlin <alexander.sverdlin@gmail.com>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@outlook.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Haylen Chu <heylenay@outlook.com>,
linux-arm-kernel@lists.infradead.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Arnd Bergmann <arnd@arndb.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Subject: [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts
Date: Sun, 9 Feb 2025 23:06:27 +0100 [thread overview]
Message-ID: <20250209220646.1090868-3-alexander.sverdlin@gmail.com> (raw)
In-Reply-To: <20250209220646.1090868-1-alexander.sverdlin@gmail.com>
Make the peripheral device tree re-usable on ARM64 platform by splitting it
into CPU-core specific and peripheral parts.
Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
into "plic" interrupt-controller numbering.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 313 ++++++++++++++++++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 305 +----------------
3 files changed, 317 insertions(+), 303 deletions(-)
create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
index 5fd14dd1b14f..bbdb30653e9a 100644
--- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
@@ -11,7 +11,7 @@ soc {
emmc: mmc@4300000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4300000 0x1000>;
- interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_EMMC>,
<&clk CLK_EMMC>;
clock-names = "core", "bus";
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
new file mode 100644
index 000000000000..53834b0658b2
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dt-bindings/clock/sophgo,cv1800.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_25m";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk: clock-controller@3002000 {
+ reg = <0x03002000 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ gpio0: gpio@3020000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio1: gpio@3021000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3021000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio2: gpio@3022000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3022000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portc: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio3: gpio@3023000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3023000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portd: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ saradc: adc@30f0000 {
+ compatible = "sophgo,cv1800b-saradc";
+ reg = <0x030f0000 0x1000>;
+ clocks = <&clk CLK_SARADC>;
+ interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ channel@0 {
+ reg = <0>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ };
+ };
+
+ i2c0: i2c@4000000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x04000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
+ clock-names = "ref", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@4010000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x04010000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
+ clock-names = "ref", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@4020000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x04020000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
+ clock-names = "ref", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@4030000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x04030000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
+ clock-names = "ref", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@4040000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x04040000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
+ clock-names = "ref", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart0: serial@4140000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04140000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@4150000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04150000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@4160000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04160000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@4170000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04170000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi0: spi@4180000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x04180000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
+ clock-names = "ssi_clk", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi1: spi@4190000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x04190000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
+ clock-names = "ssi_clk", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi2: spi@41a0000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x041a0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
+ clock-names = "ssi_clk", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi3: spi@41b0000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x041b0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
+ clock-names = "ssi_clk", "pclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart4: serial@41c0000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x041c0000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ sdhci0: mmc@4310000 {
+ compatible = "sophgo,cv1800b-dwcmshc";
+ reg = <0x4310000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_AXI4_SD0>,
+ <&clk CLK_SD0>;
+ clock-names = "core", "bus";
+ status = "disabled";
+ };
+
+ sdhci1: mmc@4320000 {
+ compatible = "sophgo,cv1800b-dwcmshc";
+ reg = <0x4320000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_AXI4_SD1>,
+ <&clk CLK_SD1>;
+ clock-names = "core", "bus";
+ status = "disabled";
+ };
+
+ dmac: dma-controller@4330000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x04330000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
+ clock-names = "core-clk", "cfgr-clk";
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ snps,block-size = <1024 1024 1024 1024
+ 1024 1024 1024 1024>;
+ snps,priority = <0 1 2 3 4 5 6 7>;
+ snps,dma-masters = <2>;
+ snps,data-width = <4>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index c18822ec849f..57a01b71aa67 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -4,9 +4,9 @@
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
-#include <dt-bindings/clock/sophgo,cv1800.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
+
+#include "cv18xx-periph.dtsi"
/ {
#address-cells = <1>;
@@ -41,310 +41,11 @@ cpu0_intc: interrupt-controller {
};
};
- osc: oscillator {
- compatible = "fixed-clock";
- clock-output-names = "osc_25m";
- #clock-cells = <0>;
- };
-
soc {
- compatible = "simple-bus";
interrupt-parent = <&plic>;
- #address-cells = <1>;
- #size-cells = <1>;
dma-noncoherent;
ranges;
- clk: clock-controller@3002000 {
- reg = <0x03002000 0x1000>;
- clocks = <&osc>;
- #clock-cells = <1>;
- };
-
- gpio0: gpio@3020000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0x3020000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- porta: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- gpio1: gpio@3021000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0x3021000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- portb: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- gpio2: gpio@3022000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0x3022000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- portc: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- gpio3: gpio@3023000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0x3023000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- portd: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- saradc: adc@30f0000 {
- compatible = "sophgo,cv1800b-saradc";
- reg = <0x030f0000 0x1000>;
- clocks = <&clk CLK_SARADC>;
- interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- channel@0 {
- reg = <0>;
- };
-
- channel@1 {
- reg = <1>;
- };
-
- channel@2 {
- reg = <2>;
- };
- };
-
- i2c0: i2c@4000000 {
- compatible = "snps,designware-i2c";
- reg = <0x04000000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
- clock-names = "ref", "pclk";
- interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- i2c1: i2c@4010000 {
- compatible = "snps,designware-i2c";
- reg = <0x04010000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
- clock-names = "ref", "pclk";
- interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- i2c2: i2c@4020000 {
- compatible = "snps,designware-i2c";
- reg = <0x04020000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
- clock-names = "ref", "pclk";
- interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- i2c3: i2c@4030000 {
- compatible = "snps,designware-i2c";
- reg = <0x04030000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
- clock-names = "ref", "pclk";
- interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- i2c4: i2c@4040000 {
- compatible = "snps,designware-i2c";
- reg = <0x04040000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
- clock-names = "ref", "pclk";
- interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- uart0: serial@4140000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04140000 0x100>;
- interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart1: serial@4150000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04150000 0x100>;
- interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart2: serial@4160000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04160000 0x100>;
- interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart3: serial@4170000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04170000 0x100>;
- interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- spi0: spi@4180000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0x04180000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
- clock-names = "ssi_clk", "pclk";
- interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- spi1: spi@4190000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0x04190000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
- clock-names = "ssi_clk", "pclk";
- interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- spi2: spi@41a0000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0x041a0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
- clock-names = "ssi_clk", "pclk";
- interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- spi3: spi@41b0000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0x041b0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
- clock-names = "ssi_clk", "pclk";
- interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- uart4: serial@41c0000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x041c0000 0x100>;
- interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- sdhci0: mmc@4310000 {
- compatible = "sophgo,cv1800b-dwcmshc";
- reg = <0x4310000 0x1000>;
- interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_AXI4_SD0>,
- <&clk CLK_SD0>;
- clock-names = "core", "bus";
- status = "disabled";
- };
-
- sdhci1: mmc@4320000 {
- compatible = "sophgo,cv1800b-dwcmshc";
- reg = <0x4320000 0x1000>;
- interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_AXI4_SD1>,
- <&clk CLK_SD1>;
- clock-names = "core", "bus";
- status = "disabled";
- };
-
- dmac: dma-controller@4330000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x04330000 0x1000>;
- interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
- clock-names = "core-clk", "cfgr-clk";
- #dma-cells = <1>;
- dma-channels = <8>;
- snps,block-size = <1024 1024 1024 1024
- 1024 1024 1024 1024>;
- snps,priority = <0 1 2 3 4 5 6 7>;
- snps,dma-masters = <2>;
- snps,data-width = <4>;
- status = "disabled";
- };
-
plic: interrupt-controller@70000000 {
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
--
2.48.1
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next prev parent reply other threads:[~2025-02-09 22:11 UTC|newest]
Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-09 22:06 [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB Alexander Sverdlin
2025-02-09 22:06 ` Alexander Sverdlin
2025-02-09 22:06 ` [PATCH 01/10] arm64: Add SOPHGO SOC family Kconfig support Alexander Sverdlin
2025-02-09 22:06 ` Alexander Sverdlin
2025-02-10 0:38 ` Chen Wang
2025-02-10 0:38 ` Chen Wang
2025-02-09 22:06 ` Alexander Sverdlin [this message]
2025-02-09 22:06 ` [PATCH 02/10] riscv: dts: sophgo: cv18xx: Split into CPU core and peripheral parts Alexander Sverdlin
2025-02-10 5:24 ` Inochi Amaoto
2025-02-10 5:24 ` Inochi Amaoto
2025-02-10 8:43 ` Krzysztof Kozlowski
2025-02-10 8:43 ` Krzysztof Kozlowski
2025-02-10 13:45 ` Alexander Sverdlin
2025-02-10 13:45 ` Alexander Sverdlin
2025-02-11 8:08 ` Krzysztof Kozlowski
2025-02-11 8:08 ` Krzysztof Kozlowski
2025-02-11 9:14 ` Alexander Sverdlin
2025-02-11 9:14 ` Alexander Sverdlin
2025-02-10 14:26 ` Alexander Sverdlin
2025-02-10 14:26 ` Alexander Sverdlin
2025-02-10 15:31 ` Krzysztof Kozlowski
2025-02-10 15:31 ` Krzysztof Kozlowski
2025-02-09 22:06 ` [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree Alexander Sverdlin
2025-02-09 22:06 ` Alexander Sverdlin
2025-02-10 5:05 ` Inochi Amaoto
2025-02-10 5:05 ` Inochi Amaoto
2025-02-10 14:16 ` Alexander Sverdlin
2025-02-10 14:16 ` Alexander Sverdlin
2025-02-10 5:26 ` Inochi Amaoto
2025-02-10 5:26 ` Inochi Amaoto
2025-02-10 8:45 ` Krzysztof Kozlowski
2025-02-10 8:45 ` Krzysztof Kozlowski
2025-02-10 15:01 ` Alexander Sverdlin
2025-02-10 15:01 ` Alexander Sverdlin
2025-02-11 8:07 ` Krzysztof Kozlowski
2025-02-11 8:07 ` Krzysztof Kozlowski
2025-02-11 9:22 ` Alexander Sverdlin
2025-02-11 9:22 ` Alexander Sverdlin
2025-02-11 12:12 ` Krzysztof Kozlowski
2025-02-11 12:12 ` Krzysztof Kozlowski
2025-02-09 22:06 ` [PATCH 04/10] arm64: dts: sophgo: Add Duo Module 01 Alexander Sverdlin
2025-02-09 22:06 ` Alexander Sverdlin
2025-02-10 5:27 ` Inochi Amaoto
2025-02-10 5:27 ` Inochi Amaoto
2025-02-10 8:47 ` Krzysztof Kozlowski
2025-02-10 8:47 ` Krzysztof Kozlowski
2025-02-09 22:06 ` [PATCH 05/10] arm64: dts: sophgo: Add Duo Module 01 Evaluation Board Alexander Sverdlin
2025-02-09 22:06 ` Alexander Sverdlin
2025-02-10 8:48 ` Krzysztof Kozlowski
2025-02-10 8:48 ` Krzysztof Kozlowski
2025-02-09 22:06 ` [PATCH 06/10] dt-bindings: mfd: syscon: Add Cvitek CV18xx rtcsys core and ctrl compatible Alexander Sverdlin
2025-02-09 22:06 ` Alexander Sverdlin
2025-02-10 5:15 ` Inochi Amaoto
2025-02-10 5:15 ` Inochi Amaoto
2025-02-10 8:48 ` Krzysztof Kozlowski
2025-02-10 8:48 ` Krzysztof Kozlowski
2025-02-10 20:30 ` Alexander Sverdlin
2025-02-10 20:30 ` Alexander Sverdlin
2025-02-10 20:40 ` Alexander Sverdlin
2025-02-10 20:40 ` Alexander Sverdlin
2025-02-09 22:06 ` [PATCH 07/10] dt-bindings: reset: sophgo: Add CV18xx reset controller Alexander Sverdlin
2025-02-09 22:06 ` Alexander Sverdlin
2025-02-10 5:36 ` Inochi Amaoto
2025-02-10 5:36 ` Inochi Amaoto
2025-02-10 8:49 ` Krzysztof Kozlowski
2025-02-10 8:49 ` Krzysztof Kozlowski
2025-02-09 22:06 ` [PATCH 08/10] riscv/arm64: dts: cv18xx: Add sysctl and reset nodes Alexander Sverdlin
2025-02-09 22:06 ` Alexander Sverdlin
2025-02-10 5:13 ` Inochi Amaoto
2025-02-10 5:13 ` Inochi Amaoto
2025-02-10 11:47 ` Alexander Sverdlin
2025-02-10 11:47 ` Alexander Sverdlin
2025-02-10 12:29 ` Inochi Amaoto
2025-02-10 12:29 ` Inochi Amaoto
2025-02-10 8:51 ` Krzysztof Kozlowski
2025-02-10 8:51 ` Krzysztof Kozlowski
2025-02-09 22:06 ` [PATCH 09/10] power: reset: cv18xx: New driver Alexander Sverdlin
2025-02-09 22:06 ` Alexander Sverdlin
2025-02-10 8:52 ` Krzysztof Kozlowski
2025-02-10 8:52 ` Krzysztof Kozlowski
2025-02-09 22:06 ` [PATCH 10/10] arm64: defconfig: Enable rudimentary Sophgo SG2000 support Alexander Sverdlin
2025-02-09 22:06 ` Alexander Sverdlin
2025-02-10 0:02 ` [PATCH 00/10] arm64 support for Milk-V Duo Module 01 EVB Chen Wang
2025-02-10 0:02 ` Chen Wang
2025-02-10 5:15 ` Inochi Amaoto
2025-02-10 5:15 ` Inochi Amaoto
2025-02-10 5:33 ` Inochi Amaoto
2025-02-10 5:33 ` Inochi Amaoto
2025-02-10 12:10 ` Alexander Sverdlin
2025-02-10 12:10 ` Alexander Sverdlin
2025-02-10 20:55 ` Alexander Sverdlin
2025-02-10 20:55 ` Alexander Sverdlin
2025-02-11 19:37 ` Alexander Sverdlin
2025-02-11 19:37 ` Alexander Sverdlin
2025-02-12 0:29 ` Inochi Amaoto
2025-02-12 0:29 ` Inochi Amaoto
2025-02-12 9:33 ` Alexander Sverdlin
2025-02-12 9:33 ` Alexander Sverdlin
2025-02-10 16:22 ` Rob Herring (Arm)
2025-02-10 16:22 ` Rob Herring (Arm)
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