From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
To: lpieralisi@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, robh@kernel.org,
bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org,
dinguyen@kernel.org, joyce.ooi@intel.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: matthew.gerlach@altera.com, peter.colberg@altera.com,
Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: [PATCH v6 4/7] arm64: dts: agilex: refactor shared dts into dtsi
Date: Tue, 11 Feb 2025 09:17:22 -0600 [thread overview]
Message-ID: <20250211151725.4133582-5-matthew.gerlach@linux.intel.com> (raw)
In-Reply-To: <20250211151725.4133582-1-matthew.gerlach@linux.intel.com>
Move common device tree from socfpga_agilex_socdk*.dts to
socfpga_agilex_socdk.dtsi.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v6:
- New patch to series.
---
.../boot/dts/intel/socfpga_agilex_socdk.dts | 62 +-----------------
.../boot/dts/intel/socfpga_agilex_socdk.dtsi | 65 +++++++++++++++++++
.../dts/intel/socfpga_agilex_socdk_nand.dts | 62 +-----------------
3 files changed, 67 insertions(+), 122 deletions(-)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index b31cfa6b802d..a970f612333a 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -3,50 +3,7 @@
* Copyright (C) 2019, Intel Corporation
*/
#include "socfpga_agilex.dtsi"
-
-/ {
- model = "SoCFPGA Agilex SoCDK";
- compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
-
- aliases {
- serial0 = &uart0;
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- ethernet2 = &gmac2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
- led0 {
- label = "hps_led0";
- gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
- };
-
- led1 {
- label = "hps_led1";
- gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
- };
-
- led2 {
- label = "hps_led2";
- gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- /* We expect the bootloader to fill in the reg */
- reg = <0 0x80000000 0 0>;
- };
-};
-
-&gpio1 {
- status = "okay";
-};
+#include "socfpga_agilex_socdk.dtsi"
&gmac0 {
status = "okay";
@@ -86,23 +43,6 @@ &mmc {
clk-phase-sd-hs = <0>, <135>;
};
-&osc1 {
- clock-frequency = <25000000>;
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- disable-over-current;
-};
-
-&watchdog0 {
- status = "okay";
-};
-
&qspi {
status = "okay";
flash@0 {
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi
new file mode 100644
index 000000000000..e0f3ff60aa33
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+/ {
+ model = "SoCFPGA Agilex SoCDK";
+ compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "hps_led0";
+ gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ led1 {
+ label = "hps_led1";
+ gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ led2 {
+ label = "hps_led2";
+ gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0x80000000 0 0>;
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
index 0f9020bd0c52..53a533cd2789 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
@@ -3,50 +3,7 @@
* Copyright (C) 2019, Intel Corporation
*/
#include "socfpga_agilex.dtsi"
-
-/ {
- model = "SoCFPGA Agilex SoCDK";
- compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
-
- aliases {
- serial0 = &uart0;
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- ethernet2 = &gmac2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
- led0 {
- label = "hps_led0";
- gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
- };
-
- led1 {
- label = "hps_led1";
- gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
- };
-
- led2 {
- label = "hps_led2";
- gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- /* We expect the bootloader to fill in the reg */
- reg = <0 0x80000000 0 0>;
- };
-};
-
-&gpio1 {
- status = "okay";
-};
+#include "socfpga_agilex_socdk.dtsi"
&gmac2 {
status = "okay";
@@ -97,20 +54,3 @@ partition@200000 {
};
};
};
-
-&osc1 {
- clock-frequency = <25000000>;
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- disable-over-current;
-};
-
-&watchdog0 {
- status = "okay";
-};
--
2.34.1
next prev parent reply other threads:[~2025-02-11 15:21 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 15:17 [PATCH v6 0/7] Add PCIe Root Port support for Agilex family of chips Matthew Gerlach
2025-02-11 15:17 ` [PATCH v6 1/7] dt-bindings: PCI: altera: Add binding for Agilex Matthew Gerlach
2025-02-11 15:17 ` [PATCH v6 2/7] arm64: dts: agilex: Fix fixed-clock schema warnings Matthew Gerlach
2025-02-12 5:56 ` Krzysztof Kozlowski
2025-02-13 17:37 ` matthew.gerlach
2025-02-13 18:03 ` Krzysztof Kozlowski
2025-02-11 15:17 ` [PATCH v6 3/7] arm64: dts: agilex: move bus@80000000 to socfpga_agilex.dtsi Matthew Gerlach
2025-02-12 5:57 ` Krzysztof Kozlowski
2025-02-11 15:17 ` Matthew Gerlach [this message]
2025-02-12 5:59 ` [PATCH v6 4/7] arm64: dts: agilex: refactor shared dts into dtsi Krzysztof Kozlowski
2025-02-11 15:17 ` [PATCH v6 5/7] arm64: dts: agilex: add dtsi for PCIe Root Port Matthew Gerlach
2025-02-11 15:17 ` [PATCH v6 6/7] arm64: dts: agilex: add dts enabling " Matthew Gerlach
2025-02-12 6:00 ` Krzysztof Kozlowski
2025-02-11 15:17 ` [PATCH v6 7/7] PCI: altera: Add Agilex support Matthew Gerlach
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250211151725.4133582-5-matthew.gerlach@linux.intel.com \
--to=matthew.gerlach@linux.intel.com \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dinguyen@kernel.org \
--cc=joyce.ooi@intel.com \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=matthew.gerlach@altera.com \
--cc=peter.colberg@altera.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.