Re: [PATCH v1 2/3] arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays

Re: [PATCH v1 2/3] arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays

[kernel test robot]

:::::: 
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
:::::: 

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250213112008.56394-3-angelogioacchino.delregno@collabora.com>
References: <20250213112008.56394-3-angelogioacchino.delregno@collabora.com>
TO: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
TO: matthias.bgg@gmail.com
CC: robh@kernel.org
CC: krzk+dt@kernel.org
CC: conor+dt@kernel.org
CC: angelogioacchino.delregno@collabora.com
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-mediatek@lists.infradead.org
CC: kernel@collabora.com
CC: pablo.sun@mediatek.com

Hi AngeloGioacchino,

kernel test robot noticed the following build warnings:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v6.14-rc2 next-20250214]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/AngeloGioacchino-Del-Regno/arm64-dts-mediatek-mt8195-Add-base-display-controller-graph/20250213-192515
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20250213112008.56394-3-angelogioacchino.delregno%40collabora.com
patch subject: [PATCH v1 2/3] arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays
:::::: branch date: 29 hours ago
:::::: commit date: 29 hours ago
config: arm64-randconfig-r072-20250214 (https://download.01.org/0day-ci/archive/20250215/202502150003.bIkvfoi2-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 14.2.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202502150003.bIkvfoi2-lkp@intel.com/

dtcheck warnings: (new ones prefixed by >>)
   arch/arm64/boot/dts/mediatek/mt8195.dtsi:3013.17-3070.5: Warning (simple_bus_reg): /soc/jpgdec-master: missing or empty reg/ranges property
   arch/arm64/boot/dts/mediatek/mt8195.dtsi:3087.17-3123.5: Warning (simple_bus_reg): /soc/jpgenc-master: missing or empty reg/ranges property
>> arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi:1513.7-1521.4: Warning (graph_child_address): /soc/syscon@1c01a000/port: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary

vim +1513 arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi

b6267a396e1cc5 AngeloGioacchino Del Regno 2022-07-04  1511  
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1512  &vdosys0 {
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13 @1513  	port {
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1514  		#address-cells = <1>;
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1515  		#size-cells = <0>;
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1516  
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1517  		vdosys0_ep_main: endpoint@0 {
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1518  			reg = <0>;
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1519  			remote-endpoint = <&ovl0_in>;
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1520  		};
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1521  	};
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1522  };
d0a8dcba3ea409 AngeloGioacchino Del Regno 2025-02-13  1523  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH v1 0/3] MediaTek MT8195/MT8395 Display Controller Graph

[AngeloGioacchino Del Regno]

This series adds a full OF Graph for the Display Controller in the
MT8195 dtsi, and configures the MT8195 Cherry devices to use it.

This was mainly done to allow different display controller paths
for the Radxa NIO 12L board (compared to Chromebooks), and this
series contains a preconfiguration for the DSI0 pipeline.

No DSI display was actually added to the Radxa board, because that's
a SBC and, even though there is a display from Radxa that can be used
with this device, it's not mandatory to use exactly that.

The NIO 12L also features an HDMI output, which will be added later
when the series adding HDMIv2/DDCv2 drivers will be merged upstream.

AngeloGioacchino Del Regno (3):
  arm64: dts: mediatek: mt8195: Add base display controller graph
  arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays
  arm64: dts: mediatek: mt8395-nio-12l: Preconfigure DSI0 pipeline

 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 184 +++++++++++++++++-
 arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 129 ++++++++++++
 .../dts/mediatek/mt8395-radxa-nio-12l.dts     |  26 +++
 3 files changed, 332 insertions(+), 7 deletions(-)

-- 
2.48.1

[PATCH v1 2/3] arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays

[AngeloGioacchino Del Regno]

The base SoC devicetree now defines a display controller graph:
connect the board specific outputs (eDP internal display, DP
external display) to fully migrate Cherry and make it finally
possible to make Chromebooks and other board types to coexist
without per-board driver modifications.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 184 +++++++++++++++++-
 1 file changed, 177 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 5056e07399e2..e70599807bb1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -297,12 +297,29 @@ &cpu7 {
 	cpu-supply = <&mt6315_6_vbuck1>;
 };
 
+&dither0_out {
+	remote-endpoint = <&dsc0_in>;
+};
+
 &dp_intf0 {
 	status = "okay";
 
-	port {
-		dp_intf0_out: endpoint {
-			remote-endpoint = <&edp_in>;
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			dp_intf0_in: endpoint {
+				remote-endpoint = <&merge0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dp_intf0_out: endpoint {
+				remote-endpoint = <&edp_in>;
+			};
 		};
 	};
 };
@@ -310,9 +327,51 @@ dp_intf0_out: endpoint {
 &dp_intf1 {
 	status = "okay";
 
-	port {
-		dp_intf1_out: endpoint {
-			remote-endpoint = <&dptx_in>;
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			dp_intf1_in: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&merge5_out>;
+			};
+		};
+
+		port@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			dp_intf1_out: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&dptx_in>;
+			};
+		};
+	};
+};
+
+&dsc0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			dsc0_in: endpoint {
+				remote-endpoint = <&dither0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dsc0_out: endpoint {
+				remote-endpoint = <&merge0_in>;
+			};
 		};
 	};
 };
@@ -357,6 +416,35 @@ panel_in: endpoint {
 	};
 };
 
+&ethdr0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			ethdr0_in: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&vdosys1_ep_ext>;
+			};
+		};
+
+		port@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			ethdr0_out: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&merge5_in>;
+			};
+		};
+	};
+};
+
 &disp_pwm0 {
 	status = "okay";
 
@@ -376,8 +464,12 @@ ports {
 		#size-cells = <0>;
 
 		port@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
 			reg = <0>;
-			dptx_in: endpoint {
+
+			dptx_in: endpoint@1 {
+				reg = <1>;
 				remote-endpoint = <&dp_intf1_out>;
 			};
 		};
@@ -511,6 +603,56 @@ pmic@34 {
 	};
 };
 
+&merge0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			merge0_in: endpoint {
+				remote-endpoint = <&dsc0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			merge0_out: endpoint {
+				remote-endpoint = <&dp_intf0_in>;
+			};
+		};
+	};
+};
+
+&merge5 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			merge5_in: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&ethdr0_out>;
+			};
+		};
+
+		port@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			merge5_out: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&dp_intf1_in>;
+			};
+		};
+	};
+};
+
 &mfg0 {
 	domain-supply = <&mt6315_7_vbuck1>;
 };
@@ -612,6 +754,10 @@ flash@0 {
 	};
 };
 
+&ovl0_in {
+	remote-endpoint = <&vdosys0_ep_main>;
+};
+
 &pcie1 {
 	status = "okay";
 
@@ -1363,6 +1509,18 @@ &uart0 {
 	status = "okay";
 };
 
+&vdosys0 {
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdosys0_ep_main: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&ovl0_in>;
+		};
+	};
+};
+
 /*
  * For the USB Type-C ports the role and alternate modes switching is
  * done by the EC so we set dr_mode to host to avoid interfering.
@@ -1385,6 +1543,18 @@ &ssusb3 {
 	status = "okay";
 };
 
+&vdosys1 {
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdosys1_ep_ext: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&ethdr0_in>;
+		};
+	};
+};
+
 &xhci0 {
 	status = "okay";
 
-- 
2.48.1