* [avpatel:riscv_unaligned_test_skip_v1 44/77] drivers/iommu/riscv/iommu.c:153:29: sparse: sparse: incorrect type in assignment (different address spaces)
@ 2025-02-16 12:25 kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2025-02-16 12:25 UTC (permalink / raw)
To: Andrew Jones; +Cc: oe-kbuild-all, Anup Patel
tree: https://github.com/avpatel/linux.git riscv_unaligned_test_skip_v1
head: a810219b42d39c2a9055150c3d3fc0677bc73e28
commit: 6ffcb04a541ee3af634b33aea0ed2fcee1ed1ab9 [44/77] iommu/riscv: Probe all icvec bits
config: riscv-randconfig-r111-20250216 (https://download.01.org/0day-ci/archive/20250216/202502162026.VcCLIIf5-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce: (https://download.01.org/0day-ci/archive/20250216/202502162026.VcCLIIf5-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202502162026.VcCLIIf5-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/iommu/riscv/iommu.c:153:29: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void *base @@ got void [noderef] __iomem * @@
drivers/iommu/riscv/iommu.c:153:29: sparse: expected void *base
drivers/iommu/riscv/iommu.c:153:29: sparse: got void [noderef] __iomem *
>> drivers/iommu/riscv/iommu.c:687:41: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected unsigned long long [usertype] *ddt_root @@ got void [noderef] __iomem * @@
drivers/iommu/riscv/iommu.c:687:41: sparse: expected unsigned long long [usertype] *ddt_root
drivers/iommu/riscv/iommu.c:687:41: sparse: got void [noderef] __iomem *
vim +153 drivers/iommu/riscv/iommu.c
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 112
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 113 /*
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 114 * Discover queue ring buffer hardware configuration, allocate in-memory
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 115 * ring buffer or use fixed I/O memory location, configure queue base register.
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 116 * Must be called before hardware queue is enabled.
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 117 *
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 118 * @queue - data structure, configured with RISCV_IOMMU_QUEUE_INIT()
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 119 * @entry_size - queue single element size in bytes.
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 120 */
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 121 static int riscv_iommu_queue_alloc(struct riscv_iommu_device *iommu,
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 122 struct riscv_iommu_queue *queue,
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 123 size_t entry_size)
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 124 {
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 125 unsigned int logsz;
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 126 u64 qb, rb;
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 127
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 128 /*
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 129 * Use WARL base register property to discover maximum allowed
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 130 * number of entries and optional fixed IO address for queue location.
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 131 */
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 132 riscv_iommu_writeq(iommu, queue->qbr, RISCV_IOMMU_QUEUE_LOG2SZ_FIELD);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 133 qb = riscv_iommu_readq(iommu, queue->qbr);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 134
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 135 /*
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 136 * Calculate and verify hardware supported queue length, as reported
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 137 * by the field LOG2SZ, where max queue length is equal to 2^(LOG2SZ + 1).
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 138 * Update queue size based on hardware supported value.
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 139 */
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 140 logsz = ilog2(queue->mask);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 141 if (logsz > FIELD_GET(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, qb))
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 142 logsz = FIELD_GET(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, qb);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 143
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 144 /*
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 145 * Use WARL base register property to discover an optional fixed IO
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 146 * address for queue ring buffer location. Otherwise allocate contiguous
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 147 * system memory.
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 148 */
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 149 if (FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb)) {
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 150 const size_t queue_size = entry_size << (logsz + 1);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 151
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 152 queue->phys = pfn_to_phys(FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb));
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 @153 queue->base = devm_ioremap(iommu->dev, queue->phys, queue_size);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 154 } else {
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 155 do {
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 156 const size_t queue_size = entry_size << (logsz + 1);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 157 const int order = get_order(queue_size);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 158
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 159 queue->base = riscv_iommu_get_pages(iommu, order);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 160 queue->phys = __pa(queue->base);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 161 } while (!queue->base && logsz-- > 0);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 162 }
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 163
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 164 if (!queue->base)
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 165 return -ENOMEM;
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 166
1200f83d66c906 Andrew Jones 2024-11-14 167 qb = riscv_iommu_phys_to_ppn(queue->phys) |
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 168 FIELD_PREP(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, logsz);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 169
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 170 /* Update base register and read back to verify hw accepted our write */
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 171 riscv_iommu_writeq(iommu, queue->qbr, qb);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 172 rb = riscv_iommu_readq(iommu, queue->qbr);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 173 if (rb != qb) {
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 174 dev_err(iommu->dev, "queue #%u allocation failed\n", queue->qid);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 175 return -ENODEV;
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 176 }
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 177
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 178 /* Update actual queue mask */
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 179 queue->mask = (2U << logsz) - 1;
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 180
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 181 dev_dbg(iommu->dev, "queue #%u allocated 2^%u entries",
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 182 queue->qid, logsz + 1);
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 183
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 184 return 0;
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 185 }
856c0cfe5c5f6a Tomasz Jeznach 2024-10-15 186
:::::: The code at line 153 was first introduced by commit
:::::: 856c0cfe5c5f6a2cc8d995872eb67bff9c68c57c iommu/riscv: Command and fault queue support
:::::: TO: Tomasz Jeznach <tjeznach@rivosinc.com>
:::::: CC: Joerg Roedel <jroedel@suse.de>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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2025-02-16 12:25 [avpatel:riscv_unaligned_test_skip_v1 44/77] drivers/iommu/riscv/iommu.c:153:29: sparse: sparse: incorrect type in assignment (different address spaces) kernel test robot
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