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From: Andrew Jones <ajones@ventanamicro.com>
To: Chao Du <duchao@eswincomputing.com>
Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
	 anup@brainfault.org, atishp@atishpatra.org,
	paul.walmsley@sifive.com,  palmer@dabbelt.com,
	aou@eecs.berkeley.edu
Subject: Re: [PATCH v2] RISC-V: KVM: Optimize comments in kvm_riscv_vcpu_isa_disable_allowed
Date: Fri, 21 Feb 2025 09:48:35 +0100	[thread overview]
Message-ID: <20250221-c503f28d950aa5268874b43c@orel> (raw)
In-Reply-To: <20250221025929.31678-1-duchao@eswincomputing.com>

On Fri, Feb 21, 2025 at 02:59:29AM +0000, Chao Du wrote:
> The comments for EXT_SVADE are a bit confusing. Optimize it to make it
> more clear.

nit: s/Optimize it to make it more clear./Clarify it./

> 
> Signed-off-by: Chao Du <duchao@eswincomputing.com>
> ---
>  arch/riscv/kvm/vcpu_onereg.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index f6d27b59c641..43ee8e33ba23 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -203,7 +203,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
>  	case KVM_RISCV_ISA_EXT_SVADE:
>  		/*
>  		 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
> -		 * Svade is not allowed to disable when the platform use Svade.
> +		 * Svade can't be disabled unless we support Svadu.
>  		 */
>  		return arch_has_hw_pte_young();
>  	default:
> -- 
> 2.34.1

Otherwise,

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: Chao Du <duchao@eswincomputing.com>
Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
	 anup@brainfault.org, atishp@atishpatra.org,
	paul.walmsley@sifive.com,  palmer@dabbelt.com,
	aou@eecs.berkeley.edu
Subject: Re: [PATCH v2] RISC-V: KVM: Optimize comments in kvm_riscv_vcpu_isa_disable_allowed
Date: Fri, 21 Feb 2025 09:48:35 +0100	[thread overview]
Message-ID: <20250221-c503f28d950aa5268874b43c@orel> (raw)
In-Reply-To: <20250221025929.31678-1-duchao@eswincomputing.com>

On Fri, Feb 21, 2025 at 02:59:29AM +0000, Chao Du wrote:
> The comments for EXT_SVADE are a bit confusing. Optimize it to make it
> more clear.

nit: s/Optimize it to make it more clear./Clarify it./

> 
> Signed-off-by: Chao Du <duchao@eswincomputing.com>
> ---
>  arch/riscv/kvm/vcpu_onereg.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index f6d27b59c641..43ee8e33ba23 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -203,7 +203,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
>  	case KVM_RISCV_ISA_EXT_SVADE:
>  		/*
>  		 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
> -		 * Svade is not allowed to disable when the platform use Svade.
> +		 * Svade can't be disabled unless we support Svadu.
>  		 */
>  		return arch_has_hw_pte_young();
>  	default:
> -- 
> 2.34.1

Otherwise,

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

  reply	other threads:[~2025-02-21  8:50 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-21  2:59 [PATCH v2] RISC-V: KVM: Optimize comments in kvm_riscv_vcpu_isa_disable_allowed Chao Du
2025-02-21  2:59 ` Chao Du
2025-02-21  8:48 ` Andrew Jones [this message]
2025-02-21  8:48   ` Andrew Jones
2025-03-20  6:16 ` Anup Patel
2025-03-20  6:16   ` Anup Patel

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