* [PATCH 0/4] Add GPIO interrupt support for Amlogic A4 and A5 SoCs
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
This patch adds GPIO interrupt support for Amlogic A4 and A5 SoCs
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Xianwei Zhao (4):
dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
irqchip: Add support for Amlogic A4 and A5 SoCs
arm64: dts: Add gpio_intc node for Amlogic-A4 SoCs
arm64: dts: Add gpio_intc node for Amlogic-A5 SoCs
.../amlogic,meson-gpio-intc.yaml | 5 +-
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 21 ++++++++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 12 +++++
drivers/irqchip/irq-meson-gpio.c | 61 ++++++++++++++++++++++
4 files changed, 98 insertions(+), 1 deletion(-)
---
base-commit: 953913df9c3ab6f496c6facd5aa7fc9f2f847ac2
change-id: 20241213-irqchip-gpio-a4-a5-80c50a1456c4
Best regards,
--
Xianwei Zhao <xianwei.zhao@amlogic.com>
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 0/4] Add GPIO interrupt support for Amlogic A4 and A5 SoCs
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
This patch adds GPIO interrupt support for Amlogic A4 and A5 SoCs
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Xianwei Zhao (4):
dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
irqchip: Add support for Amlogic A4 and A5 SoCs
arm64: dts: Add gpio_intc node for Amlogic-A4 SoCs
arm64: dts: Add gpio_intc node for Amlogic-A5 SoCs
.../amlogic,meson-gpio-intc.yaml | 5 +-
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 21 ++++++++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 12 +++++
drivers/irqchip/irq-meson-gpio.c | 61 ++++++++++++++++++++++
4 files changed, 98 insertions(+), 1 deletion(-)
---
base-commit: 953913df9c3ab6f496c6facd5aa7fc9f2f847ac2
change-id: 20241213-irqchip-gpio-a4-a5-80c50a1456c4
Best regards,
--
Xianwei Zhao <xianwei.zhao@amlogic.com>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 1/4] dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
(?)
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
-1 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
Update dt-binding document for GPIO interrupt controller
of Amlogic A4 and A5 SoCs
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
.../bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
index a93744763787..03548ee695bd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
@@ -35,6 +35,9 @@ properties:
- amlogic,meson-sm1-gpio-intc
- amlogic,meson-a1-gpio-intc
- amlogic,meson-s4-gpio-intc
+ - amlogic,a4-gpio-intc
+ - amlogic,a4-gpio-ao-intc
+ - amlogic,a5-gpio-intc
- amlogic,c3-gpio-intc
- amlogic,t7-gpio-intc
- const: amlogic,meson-gpio-intc
@@ -49,7 +52,7 @@ properties:
amlogic,channel-interrupts:
description: Array with the upstream hwirq numbers
- minItems: 8
+ minItems: 2
maxItems: 12
$ref: /schemas/types.yaml#/definitions/uint32-array
--
2.37.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 1/4] dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Update dt-binding document for GPIO interrupt controller
of Amlogic A4 and A5 SoCs
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
.../bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
index a93744763787..03548ee695bd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
@@ -35,6 +35,9 @@ properties:
- amlogic,meson-sm1-gpio-intc
- amlogic,meson-a1-gpio-intc
- amlogic,meson-s4-gpio-intc
+ - amlogic,a4-gpio-intc
+ - amlogic,a4-gpio-ao-intc
+ - amlogic,a5-gpio-intc
- amlogic,c3-gpio-intc
- amlogic,t7-gpio-intc
- const: amlogic,meson-gpio-intc
@@ -49,7 +52,7 @@ properties:
amlogic,channel-interrupts:
description: Array with the upstream hwirq numbers
- minItems: 8
+ minItems: 2
maxItems: 12
$ref: /schemas/types.yaml#/definitions/uint32-array
--
2.37.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 1/4] dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Update dt-binding document for GPIO interrupt controller
of Amlogic A4 and A5 SoCs
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
.../bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
index a93744763787..03548ee695bd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
@@ -35,6 +35,9 @@ properties:
- amlogic,meson-sm1-gpio-intc
- amlogic,meson-a1-gpio-intc
- amlogic,meson-s4-gpio-intc
+ - amlogic,a4-gpio-intc
+ - amlogic,a4-gpio-ao-intc
+ - amlogic,a5-gpio-intc
- amlogic,c3-gpio-intc
- amlogic,t7-gpio-intc
- const: amlogic,meson-gpio-intc
@@ -49,7 +52,7 @@ properties:
amlogic,channel-interrupts:
description: Array with the upstream hwirq numbers
- minItems: 8
+ minItems: 2
maxItems: 12
$ref: /schemas/types.yaml#/definitions/uint32-array
--
2.37.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 1/4] dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
@ 2025-02-21 21:08 ` Rob Herring
-1 siblings, 0 replies; 23+ messages in thread
From: Rob Herring @ 2025-02-21 21:08 UTC (permalink / raw)
To: Xianwei Zhao
Cc: Thomas Gleixner, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit, linux-kernel, devicetree, linux-arm-kernel,
linux-amlogic
On Wed, Feb 19, 2025 at 03:29:03PM +0800, Xianwei Zhao wrote:
> Update dt-binding document for GPIO interrupt controller
> of Amlogic A4 and A5 SoCs
>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> ---
> .../bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
> index a93744763787..03548ee695bd 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
> @@ -35,6 +35,9 @@ properties:
> - amlogic,meson-sm1-gpio-intc
> - amlogic,meson-a1-gpio-intc
> - amlogic,meson-s4-gpio-intc
> + - amlogic,a4-gpio-intc
> + - amlogic,a4-gpio-ao-intc
> + - amlogic,a5-gpio-intc
> - amlogic,c3-gpio-intc
> - amlogic,t7-gpio-intc
> - const: amlogic,meson-gpio-intc
> @@ -49,7 +52,7 @@ properties:
>
> amlogic,channel-interrupts:
> description: Array with the upstream hwirq numbers
> - minItems: 8
> + minItems: 2
There should be an if/then schema that retains 8 as the minimum for the
existing cases.
> maxItems: 12
> $ref: /schemas/types.yaml#/definitions/uint32-array
>
>
> --
> 2.37.1
>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/4] dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
@ 2025-02-21 21:08 ` Rob Herring
0 siblings, 0 replies; 23+ messages in thread
From: Rob Herring @ 2025-02-21 21:08 UTC (permalink / raw)
To: Xianwei Zhao
Cc: Thomas Gleixner, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit, linux-kernel, devicetree, linux-arm-kernel,
linux-amlogic
On Wed, Feb 19, 2025 at 03:29:03PM +0800, Xianwei Zhao wrote:
> Update dt-binding document for GPIO interrupt controller
> of Amlogic A4 and A5 SoCs
>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> ---
> .../bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
> index a93744763787..03548ee695bd 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
> @@ -35,6 +35,9 @@ properties:
> - amlogic,meson-sm1-gpio-intc
> - amlogic,meson-a1-gpio-intc
> - amlogic,meson-s4-gpio-intc
> + - amlogic,a4-gpio-intc
> + - amlogic,a4-gpio-ao-intc
> + - amlogic,a5-gpio-intc
> - amlogic,c3-gpio-intc
> - amlogic,t7-gpio-intc
> - const: amlogic,meson-gpio-intc
> @@ -49,7 +52,7 @@ properties:
>
> amlogic,channel-interrupts:
> description: Array with the upstream hwirq numbers
> - minItems: 8
> + minItems: 2
There should be an if/then schema that retains 8 as the minimum for the
existing cases.
> maxItems: 12
> $ref: /schemas/types.yaml#/definitions/uint32-array
>
>
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/4] dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
2025-02-21 21:08 ` Rob Herring
@ 2025-02-24 1:57 ` Xianwei Zhao
-1 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao @ 2025-02-24 1:57 UTC (permalink / raw)
To: Rob Herring
Cc: Thomas Gleixner, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit, linux-kernel, devicetree, linux-arm-kernel,
linux-amlogic
Hi Rob,
Thanks for your advice.
On 2025/2/22 05:08, Rob Herring wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed, Feb 19, 2025 at 03:29:03PM +0800, Xianwei Zhao wrote:
>> Update dt-binding document for GPIO interrupt controller
>> of Amlogic A4 and A5 SoCs
>>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> .../bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml | 5 ++++-
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
>> index a93744763787..03548ee695bd 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
>> @@ -35,6 +35,9 @@ properties:
>> - amlogic,meson-sm1-gpio-intc
>> - amlogic,meson-a1-gpio-intc
>> - amlogic,meson-s4-gpio-intc
>> + - amlogic,a4-gpio-intc
>> + - amlogic,a4-gpio-ao-intc
>> + - amlogic,a5-gpio-intc
>> - amlogic,c3-gpio-intc
>> - amlogic,t7-gpio-intc
>> - const: amlogic,meson-gpio-intc
>> @@ -49,7 +52,7 @@ properties:
>>
>> amlogic,channel-interrupts:
>> description: Array with the upstream hwirq numbers
>> - minItems: 8
>> + minItems: 2
>
> There should be an if/then schema that retains 8 as the minimum for the
> existing cases.
>
Will do.
>> maxItems: 12
>> $ref: /schemas/types.yaml#/definitions/uint32-array
>>
>>
>> --
>> 2.37.1
>>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 1/4] dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
@ 2025-02-24 1:57 ` Xianwei Zhao
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao @ 2025-02-24 1:57 UTC (permalink / raw)
To: Rob Herring
Cc: Thomas Gleixner, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit, linux-kernel, devicetree, linux-arm-kernel,
linux-amlogic
Hi Rob,
Thanks for your advice.
On 2025/2/22 05:08, Rob Herring wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed, Feb 19, 2025 at 03:29:03PM +0800, Xianwei Zhao wrote:
>> Update dt-binding document for GPIO interrupt controller
>> of Amlogic A4 and A5 SoCs
>>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> .../bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml | 5 ++++-
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
>> index a93744763787..03548ee695bd 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
>> @@ -35,6 +35,9 @@ properties:
>> - amlogic,meson-sm1-gpio-intc
>> - amlogic,meson-a1-gpio-intc
>> - amlogic,meson-s4-gpio-intc
>> + - amlogic,a4-gpio-intc
>> + - amlogic,a4-gpio-ao-intc
>> + - amlogic,a5-gpio-intc
>> - amlogic,c3-gpio-intc
>> - amlogic,t7-gpio-intc
>> - const: amlogic,meson-gpio-intc
>> @@ -49,7 +52,7 @@ properties:
>>
>> amlogic,channel-interrupts:
>> description: Array with the upstream hwirq numbers
>> - minItems: 8
>> + minItems: 2
>
> There should be an if/then schema that retains 8 as the minimum for the
> existing cases.
>
Will do.
>> maxItems: 12
>> $ref: /schemas/types.yaml#/definitions/uint32-array
>>
>>
>> --
>> 2.37.1
>>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs
2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
(?)
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
-1 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
The Amlogic A4 SoCs support 12 GPIO IRQ lines and 2 AO GPIO IRQ lines,
A5 SoCs support 12 GPIO IRQ lines, details are as below.
A4 IRQ Number:
- 72:55 18 pins on bank T
- 54:32 23 pins on bank X
- 31:16 16 pins on bank D
- 15:14 2 pins on bank E
- 13:0 14 pins on bank B
A4 AO IRQ Number:
- 7 1 pin on bank TESTN
- 6:0 7 pins on bank AO
A5 IRQ Number:
- 98 1 pin on bank TESTN
- 97:82 16 pins on bank Z
- 81:62 20 pins on bank X
- 61:48 14 pins on bank T
- 47:32 16 pins on bank D
- 31:27 5 pins on bank H
- 26:25 2 pins on bank E
- 24:14 11 pins on bank C
- 13:0 14 pins on bank B
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 61 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index cd789fa51519..1ef391274653 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -28,6 +28,8 @@
#define REG_PIN_A1_SEL 0x04
/* Used for s4 chips */
#define REG_EDGE_POL_S4 0x1c
+/* Used for A4 AO chips */
+#define REG_EDGE_POL_AO 0x08
/*
* Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
@@ -57,6 +59,8 @@ static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
unsigned int type, u32 *channel_hwirq);
static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
unsigned int type, u32 *channel_hwirq);
+static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int type, u32 *channel_hwirq);
struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
@@ -105,6 +109,17 @@ struct meson_gpio_irq_params {
.pin_sel_mask = 0x7f, \
.nr_channels = 8, \
+#define INIT_MESON_A4_AO_COMMON_DATA(irqs) \
+ INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
+ meson_a1_gpio_irq_sel_pin, \
+ meson_ao_gpio_irq_set_type) \
+ .support_edge_both = true, \
+ .edge_both_offset = 0, \
+ .edge_single_offset = 12, \
+ .pol_low_offset = 0, \
+ .pin_sel_mask = 0xff, \
+ .nr_channels = 2, \
+
#define INIT_MESON_S4_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
meson_a1_gpio_irq_sel_pin, \
@@ -146,6 +161,18 @@ static const struct meson_gpio_irq_params a1_params = {
INIT_MESON_A1_COMMON_DATA(62)
};
+static const struct meson_gpio_irq_params a4_params = {
+ INIT_MESON_S4_COMMON_DATA(81)
+};
+
+static const struct meson_gpio_irq_params a4_ao_params = {
+ INIT_MESON_A4_AO_COMMON_DATA(8)
+};
+
+static const struct meson_gpio_irq_params a5_params = {
+ INIT_MESON_S4_COMMON_DATA(99)
+};
+
static const struct meson_gpio_irq_params s4_params = {
INIT_MESON_S4_COMMON_DATA(82)
};
@@ -168,6 +195,9 @@ static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
+ { .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params },
+ { .compatible = "amlogic,a4-gpio-intc", .data = &a4_params },
+ { .compatible = "amlogic,a5-gpio-intc", .data = &a5_params },
{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
{ .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
{ }
@@ -383,6 +413,37 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
return 0;
};
+static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int type, u32 *channel_hwirq)
+{
+ u32 val = 0;
+ unsigned int idx;
+
+ idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
+
+ type &= IRQ_TYPE_SENSE_MASK;
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
+
+ if (type == IRQ_TYPE_EDGE_BOTH) {
+ val |= BIT(ctl->params->edge_both_offset + (idx));
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
+ BIT(ctl->params->edge_both_offset + (idx)), val);
+ return 0;
+ }
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->pol_low_offset + idx);
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->edge_single_offset + idx);
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+ BIT(idx) | BIT(12 + idx), val);
+
+ return 0;
+};
+
static unsigned int meson_gpio_irq_type_output(unsigned int type)
{
unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
--
2.37.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
The Amlogic A4 SoCs support 12 GPIO IRQ lines and 2 AO GPIO IRQ lines,
A5 SoCs support 12 GPIO IRQ lines, details are as below.
A4 IRQ Number:
- 72:55 18 pins on bank T
- 54:32 23 pins on bank X
- 31:16 16 pins on bank D
- 15:14 2 pins on bank E
- 13:0 14 pins on bank B
A4 AO IRQ Number:
- 7 1 pin on bank TESTN
- 6:0 7 pins on bank AO
A5 IRQ Number:
- 98 1 pin on bank TESTN
- 97:82 16 pins on bank Z
- 81:62 20 pins on bank X
- 61:48 14 pins on bank T
- 47:32 16 pins on bank D
- 31:27 5 pins on bank H
- 26:25 2 pins on bank E
- 24:14 11 pins on bank C
- 13:0 14 pins on bank B
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 61 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index cd789fa51519..1ef391274653 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -28,6 +28,8 @@
#define REG_PIN_A1_SEL 0x04
/* Used for s4 chips */
#define REG_EDGE_POL_S4 0x1c
+/* Used for A4 AO chips */
+#define REG_EDGE_POL_AO 0x08
/*
* Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
@@ -57,6 +59,8 @@ static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
unsigned int type, u32 *channel_hwirq);
static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
unsigned int type, u32 *channel_hwirq);
+static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int type, u32 *channel_hwirq);
struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
@@ -105,6 +109,17 @@ struct meson_gpio_irq_params {
.pin_sel_mask = 0x7f, \
.nr_channels = 8, \
+#define INIT_MESON_A4_AO_COMMON_DATA(irqs) \
+ INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
+ meson_a1_gpio_irq_sel_pin, \
+ meson_ao_gpio_irq_set_type) \
+ .support_edge_both = true, \
+ .edge_both_offset = 0, \
+ .edge_single_offset = 12, \
+ .pol_low_offset = 0, \
+ .pin_sel_mask = 0xff, \
+ .nr_channels = 2, \
+
#define INIT_MESON_S4_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
meson_a1_gpio_irq_sel_pin, \
@@ -146,6 +161,18 @@ static const struct meson_gpio_irq_params a1_params = {
INIT_MESON_A1_COMMON_DATA(62)
};
+static const struct meson_gpio_irq_params a4_params = {
+ INIT_MESON_S4_COMMON_DATA(81)
+};
+
+static const struct meson_gpio_irq_params a4_ao_params = {
+ INIT_MESON_A4_AO_COMMON_DATA(8)
+};
+
+static const struct meson_gpio_irq_params a5_params = {
+ INIT_MESON_S4_COMMON_DATA(99)
+};
+
static const struct meson_gpio_irq_params s4_params = {
INIT_MESON_S4_COMMON_DATA(82)
};
@@ -168,6 +195,9 @@ static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
+ { .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params },
+ { .compatible = "amlogic,a4-gpio-intc", .data = &a4_params },
+ { .compatible = "amlogic,a5-gpio-intc", .data = &a5_params },
{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
{ .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
{ }
@@ -383,6 +413,37 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
return 0;
};
+static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int type, u32 *channel_hwirq)
+{
+ u32 val = 0;
+ unsigned int idx;
+
+ idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
+
+ type &= IRQ_TYPE_SENSE_MASK;
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
+
+ if (type == IRQ_TYPE_EDGE_BOTH) {
+ val |= BIT(ctl->params->edge_both_offset + (idx));
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
+ BIT(ctl->params->edge_both_offset + (idx)), val);
+ return 0;
+ }
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->pol_low_offset + idx);
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->edge_single_offset + idx);
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+ BIT(idx) | BIT(12 + idx), val);
+
+ return 0;
+};
+
static unsigned int meson_gpio_irq_type_output(unsigned int type)
{
unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
--
2.37.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
The Amlogic A4 SoCs support 12 GPIO IRQ lines and 2 AO GPIO IRQ lines,
A5 SoCs support 12 GPIO IRQ lines, details are as below.
A4 IRQ Number:
- 72:55 18 pins on bank T
- 54:32 23 pins on bank X
- 31:16 16 pins on bank D
- 15:14 2 pins on bank E
- 13:0 14 pins on bank B
A4 AO IRQ Number:
- 7 1 pin on bank TESTN
- 6:0 7 pins on bank AO
A5 IRQ Number:
- 98 1 pin on bank TESTN
- 97:82 16 pins on bank Z
- 81:62 20 pins on bank X
- 61:48 14 pins on bank T
- 47:32 16 pins on bank D
- 31:27 5 pins on bank H
- 26:25 2 pins on bank E
- 24:14 11 pins on bank C
- 13:0 14 pins on bank B
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 61 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index cd789fa51519..1ef391274653 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -28,6 +28,8 @@
#define REG_PIN_A1_SEL 0x04
/* Used for s4 chips */
#define REG_EDGE_POL_S4 0x1c
+/* Used for A4 AO chips */
+#define REG_EDGE_POL_AO 0x08
/*
* Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
@@ -57,6 +59,8 @@ static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
unsigned int type, u32 *channel_hwirq);
static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
unsigned int type, u32 *channel_hwirq);
+static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int type, u32 *channel_hwirq);
struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
@@ -105,6 +109,17 @@ struct meson_gpio_irq_params {
.pin_sel_mask = 0x7f, \
.nr_channels = 8, \
+#define INIT_MESON_A4_AO_COMMON_DATA(irqs) \
+ INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
+ meson_a1_gpio_irq_sel_pin, \
+ meson_ao_gpio_irq_set_type) \
+ .support_edge_both = true, \
+ .edge_both_offset = 0, \
+ .edge_single_offset = 12, \
+ .pol_low_offset = 0, \
+ .pin_sel_mask = 0xff, \
+ .nr_channels = 2, \
+
#define INIT_MESON_S4_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
meson_a1_gpio_irq_sel_pin, \
@@ -146,6 +161,18 @@ static const struct meson_gpio_irq_params a1_params = {
INIT_MESON_A1_COMMON_DATA(62)
};
+static const struct meson_gpio_irq_params a4_params = {
+ INIT_MESON_S4_COMMON_DATA(81)
+};
+
+static const struct meson_gpio_irq_params a4_ao_params = {
+ INIT_MESON_A4_AO_COMMON_DATA(8)
+};
+
+static const struct meson_gpio_irq_params a5_params = {
+ INIT_MESON_S4_COMMON_DATA(99)
+};
+
static const struct meson_gpio_irq_params s4_params = {
INIT_MESON_S4_COMMON_DATA(82)
};
@@ -168,6 +195,9 @@ static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
+ { .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params },
+ { .compatible = "amlogic,a4-gpio-intc", .data = &a4_params },
+ { .compatible = "amlogic,a5-gpio-intc", .data = &a5_params },
{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
{ .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
{ }
@@ -383,6 +413,37 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
return 0;
};
+static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int type, u32 *channel_hwirq)
+{
+ u32 val = 0;
+ unsigned int idx;
+
+ idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
+
+ type &= IRQ_TYPE_SENSE_MASK;
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
+
+ if (type == IRQ_TYPE_EDGE_BOTH) {
+ val |= BIT(ctl->params->edge_both_offset + (idx));
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
+ BIT(ctl->params->edge_both_offset + (idx)), val);
+ return 0;
+ }
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->pol_low_offset + idx);
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->edge_single_offset + idx);
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+ BIT(idx) | BIT(12 + idx), val);
+
+ return 0;
+};
+
static unsigned int meson_gpio_irq_type_output(unsigned int type)
{
unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
--
2.37.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs
2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
@ 2025-02-21 9:07 ` Thomas Gleixner
-1 siblings, 0 replies; 23+ messages in thread
From: Thomas Gleixner @ 2025-02-21 9:07 UTC (permalink / raw)
To: Xianwei Zhao via B4 Relay, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
On Wed, Feb 19 2025 at 15:29, Xianwei Zhao via wrote:
>
> +static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
> + unsigned int type, u32 *channel_hwirq)
> +{
> + u32 val = 0;
> + unsigned int idx;
> +
> + idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
> +
> + type &= IRQ_TYPE_SENSE_MASK;
> +
> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
> +
> + if (type == IRQ_TYPE_EDGE_BOTH) {
> + val |= BIT(ctl->params->edge_both_offset + (idx));
> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
> + BIT(ctl->params->edge_both_offset + (idx)), val);
> + return 0;
> + }
> +
> + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
> + val |= BIT(ctl->params->pol_low_offset + idx);
> +
> + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
> + val |= BIT(ctl->params->edge_single_offset + idx);
> +
> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
> + BIT(idx) | BIT(12 + idx), val);
> +
> + return 0;
> +};
This function is a full copy of meson_s4_gpio_irq_set_type() with the
only difference of:
s/REG_EDGE_POL_S4/REG_EDGE_POL_AO/
Can you please stick that register offset into the parameter structure
and use the function for both variants?
Thanks,
tglx
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs
@ 2025-02-21 9:07 ` Thomas Gleixner
0 siblings, 0 replies; 23+ messages in thread
From: Thomas Gleixner @ 2025-02-21 9:07 UTC (permalink / raw)
To: Xianwei Zhao via B4 Relay, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
On Wed, Feb 19 2025 at 15:29, Xianwei Zhao via wrote:
>
> +static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
> + unsigned int type, u32 *channel_hwirq)
> +{
> + u32 val = 0;
> + unsigned int idx;
> +
> + idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
> +
> + type &= IRQ_TYPE_SENSE_MASK;
> +
> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
> +
> + if (type == IRQ_TYPE_EDGE_BOTH) {
> + val |= BIT(ctl->params->edge_both_offset + (idx));
> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
> + BIT(ctl->params->edge_both_offset + (idx)), val);
> + return 0;
> + }
> +
> + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
> + val |= BIT(ctl->params->pol_low_offset + idx);
> +
> + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
> + val |= BIT(ctl->params->edge_single_offset + idx);
> +
> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
> + BIT(idx) | BIT(12 + idx), val);
> +
> + return 0;
> +};
This function is a full copy of meson_s4_gpio_irq_set_type() with the
only difference of:
s/REG_EDGE_POL_S4/REG_EDGE_POL_AO/
Can you please stick that register offset into the parameter structure
and use the function for both variants?
Thanks,
tglx
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs
2025-02-21 9:07 ` Thomas Gleixner
@ 2025-02-21 9:40 ` Xianwei Zhao
-1 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao @ 2025-02-21 9:40 UTC (permalink / raw)
To: Thomas Gleixner, Xianwei Zhao via B4 Relay, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic
Hi Thomas,
Thank you for your advice.
On 2025/2/21 17:07, Thomas Gleixner wrote:
> [You don't often get email from tglx@linutronix.de. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> [ EXTERNAL EMAIL ]
>
> On Wed, Feb 19 2025 at 15:29, Xianwei Zhao via wrote:
>>
>> +static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
>> + unsigned int type, u32 *channel_hwirq)
>> +{
>> + u32 val = 0;
>> + unsigned int idx;
>> +
>> + idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
>> +
>> + type &= IRQ_TYPE_SENSE_MASK;
>> +
>> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
>> +
>> + if (type == IRQ_TYPE_EDGE_BOTH) {
>> + val |= BIT(ctl->params->edge_both_offset + (idx));
>> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
>> + BIT(ctl->params->edge_both_offset + (idx)), val);
>> + return 0;
>> + }
>> +
>> + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
>> + val |= BIT(ctl->params->pol_low_offset + idx);
>> +
>> + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
>> + val |= BIT(ctl->params->edge_single_offset + idx);
>> +
>> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
>> + BIT(idx) | BIT(12 + idx), val);
>> +
>> + return 0;
>> +};
>
> This function is a full copy of meson_s4_gpio_irq_set_type() with the
> only difference of:
>
> s/REG_EDGE_POL_S4/REG_EDGE_POL_AO/
>
> Can you please stick that register offset into the parameter structure
> and use the function for both variants?
>
> Thanks,
>
Will do.
> tglx
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs
@ 2025-02-21 9:40 ` Xianwei Zhao
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao @ 2025-02-21 9:40 UTC (permalink / raw)
To: Thomas Gleixner, Xianwei Zhao via B4 Relay, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic
Hi Thomas,
Thank you for your advice.
On 2025/2/21 17:07, Thomas Gleixner wrote:
> [You don't often get email from tglx@linutronix.de. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> [ EXTERNAL EMAIL ]
>
> On Wed, Feb 19 2025 at 15:29, Xianwei Zhao via wrote:
>>
>> +static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
>> + unsigned int type, u32 *channel_hwirq)
>> +{
>> + u32 val = 0;
>> + unsigned int idx;
>> +
>> + idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
>> +
>> + type &= IRQ_TYPE_SENSE_MASK;
>> +
>> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
>> +
>> + if (type == IRQ_TYPE_EDGE_BOTH) {
>> + val |= BIT(ctl->params->edge_both_offset + (idx));
>> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
>> + BIT(ctl->params->edge_both_offset + (idx)), val);
>> + return 0;
>> + }
>> +
>> + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
>> + val |= BIT(ctl->params->pol_low_offset + idx);
>> +
>> + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
>> + val |= BIT(ctl->params->edge_single_offset + idx);
>> +
>> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
>> + BIT(idx) | BIT(12 + idx), val);
>> +
>> + return 0;
>> +};
>
> This function is a full copy of meson_s4_gpio_irq_set_type() with the
> only difference of:
>
> s/REG_EDGE_POL_S4/REG_EDGE_POL_AO/
>
> Can you please stick that register offset into the parameter structure
> and use the function for both variants?
>
> Thanks,
>
Will do.
> tglx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 3/4] arm64: dts: Add gpio_intc node for Amlogic-A4 SoCs
2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
(?)
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
-1 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
Add GPIO interrupt controller device.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index de10e7aebf21..a06838552f21 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -48,3 +48,24 @@ pwrc: power-controller {
};
};
};
+
+&apb {
+ gpio_intc: interrupt-controller@4080 {
+ compatible = "amlogic,a4-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x4080 0x0 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts =
+ <10 11 12 13 14 15 16 17 18 19 20 21>;
+ };
+
+ gpio_ao_intc: interrupt-controller@8e72c {
+ compatible = "amlogic,a4-gpio-ao-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x8e72c 0x0 0x0c>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts = <140 141>;
+ };
+};
--
2.37.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 3/4] arm64: dts: Add gpio_intc node for Amlogic-A4 SoCs
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Add GPIO interrupt controller device.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index de10e7aebf21..a06838552f21 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -48,3 +48,24 @@ pwrc: power-controller {
};
};
};
+
+&apb {
+ gpio_intc: interrupt-controller@4080 {
+ compatible = "amlogic,a4-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x4080 0x0 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts =
+ <10 11 12 13 14 15 16 17 18 19 20 21>;
+ };
+
+ gpio_ao_intc: interrupt-controller@8e72c {
+ compatible = "amlogic,a4-gpio-ao-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x8e72c 0x0 0x0c>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts = <140 141>;
+ };
+};
--
2.37.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 3/4] arm64: dts: Add gpio_intc node for Amlogic-A4 SoCs
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Add GPIO interrupt controller device.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index de10e7aebf21..a06838552f21 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -48,3 +48,24 @@ pwrc: power-controller {
};
};
};
+
+&apb {
+ gpio_intc: interrupt-controller@4080 {
+ compatible = "amlogic,a4-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x4080 0x0 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts =
+ <10 11 12 13 14 15 16 17 18 19 20 21>;
+ };
+
+ gpio_ao_intc: interrupt-controller@8e72c {
+ compatible = "amlogic,a4-gpio-ao-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x8e72c 0x0 0x0c>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts = <140 141>;
+ };
+};
--
2.37.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 4/4] arm64: dts: Add gpio_intc node for Amlogic-A5 SoCs
2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
(?)
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
-1 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
Add GPIO interrupt controller device.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
index 17a6316de891..32ed1776891b 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -48,3 +48,15 @@ pwrc: power-controller {
};
};
};
+
+&apb {
+ gpio_intc: interrupt-controller@4080 {
+ compatible = "amlogic,a5-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x4080 0x0 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts =
+ <10 11 12 13 14 15 16 17 18 19 20 21>;
+ };
+};
--
2.37.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 4/4] arm64: dts: Add gpio_intc node for Amlogic-A5 SoCs
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Add GPIO interrupt controller device.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
index 17a6316de891..32ed1776891b 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -48,3 +48,15 @@ pwrc: power-controller {
};
};
};
+
+&apb {
+ gpio_intc: interrupt-controller@4080 {
+ compatible = "amlogic,a5-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x4080 0x0 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts =
+ <10 11 12 13 14 15 16 17 18 19 20 21>;
+ };
+};
--
2.37.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 4/4] arm64: dts: Add gpio_intc node for Amlogic-A5 SoCs
@ 2025-02-19 7:29 ` Xianwei Zhao via B4 Relay
0 siblings, 0 replies; 23+ messages in thread
From: Xianwei Zhao via B4 Relay @ 2025-02-19 7:29 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Heiner Kallweit
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-amlogic,
Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Add GPIO interrupt controller device.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
index 17a6316de891..32ed1776891b 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -48,3 +48,15 @@ pwrc: power-controller {
};
};
};
+
+&apb {
+ gpio_intc: interrupt-controller@4080 {
+ compatible = "amlogic,a5-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x4080 0x0 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts =
+ <10 11 12 13 14 15 16 17 18 19 20 21>;
+ };
+};
--
2.37.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 23+ messages in thread