From: Simon Horman <horms@kernel.org>
To: Grzegorz Nitka <grzegorz.nitka@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
Karol Kolacinski <karol.kolacinski@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
Milena Olech <milena.olech@intel.com>
Subject: Re: [Intel-wired-lan] [PATCH iwl-net v1] ice: fix lane number calculation
Date: Thu, 27 Feb 2025 17:27:23 +0000 [thread overview]
Message-ID: <20250227172723.GG1615191@kernel.org> (raw)
In-Reply-To: <20250225095021.GK1615191@kernel.org>
On Tue, Feb 25, 2025 at 09:50:21AM +0000, Simon Horman wrote:
> On Fri, Feb 21, 2025 at 10:39:49AM +0100, Grzegorz Nitka wrote:
> > E82X adapters do not have sequential IDs, lane number is PF ID.
> >
> > Add check for ICE_MAC_GENERIC and skip checking port options.
>
> This I see.
Sorry, this was part of an earlier draft. Please ignore.
>
> >
> > Also, adjust logical port number for specific E825 device with external
> > PHY support (PCI device id 0x579F). For this particular device,
> > with 2x25G (PHY0) and 2x10G (PHY1) port configuration, modification of
> > pf_id -> lane_number mapping is required. PF IDs on the 2nd PHY start
> > from 4 in such scenario. Otherwise, the lane number cannot be
> > determined correctly, leading to PTP init errors during PF initialization.
> >
> > Fixes: 258f5f9058159 ("ice: Add correct PHY lane assignment")
> > Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
> > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
> > Reviewed-by: Milena Olech <milena.olech@intel.com>
>
> Reviewed-by: Simon Horman <horms@kernel.org>
I only meant to send this part :)
WARNING: multiple messages have this Message-ID (diff)
From: Simon Horman <horms@kernel.org>
To: Grzegorz Nitka <grzegorz.nitka@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
Karol Kolacinski <karol.kolacinski@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
Milena Olech <milena.olech@intel.com>
Subject: Re: [PATCH iwl-net v1] ice: fix lane number calculation
Date: Thu, 27 Feb 2025 17:27:23 +0000 [thread overview]
Message-ID: <20250227172723.GG1615191@kernel.org> (raw)
In-Reply-To: <20250225095021.GK1615191@kernel.org>
On Tue, Feb 25, 2025 at 09:50:21AM +0000, Simon Horman wrote:
> On Fri, Feb 21, 2025 at 10:39:49AM +0100, Grzegorz Nitka wrote:
> > E82X adapters do not have sequential IDs, lane number is PF ID.
> >
> > Add check for ICE_MAC_GENERIC and skip checking port options.
>
> This I see.
Sorry, this was part of an earlier draft. Please ignore.
>
> >
> > Also, adjust logical port number for specific E825 device with external
> > PHY support (PCI device id 0x579F). For this particular device,
> > with 2x25G (PHY0) and 2x10G (PHY1) port configuration, modification of
> > pf_id -> lane_number mapping is required. PF IDs on the 2nd PHY start
> > from 4 in such scenario. Otherwise, the lane number cannot be
> > determined correctly, leading to PTP init errors during PF initialization.
> >
> > Fixes: 258f5f9058159 ("ice: Add correct PHY lane assignment")
> > Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
> > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
> > Reviewed-by: Milena Olech <milena.olech@intel.com>
>
> Reviewed-by: Simon Horman <horms@kernel.org>
I only meant to send this part :)
next prev parent reply other threads:[~2025-02-27 17:27 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-21 9:39 [Intel-wired-lan] [PATCH iwl-net v1] ice: fix lane number calculation Grzegorz Nitka
2025-02-21 9:39 ` Grzegorz Nitka
2025-02-25 9:50 ` [Intel-wired-lan] " Simon Horman
2025-02-25 9:50 ` Simon Horman
2025-02-27 17:27 ` Simon Horman [this message]
2025-02-27 17:27 ` Simon Horman
2025-10-03 7:45 ` [Intel-wired-lan] " Rinitha, SX
2025-10-03 7:45 ` Rinitha, SX
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250227172723.GG1615191@kernel.org \
--to=horms@kernel.org \
--cc=grzegorz.nitka@intel.com \
--cc=intel-wired-lan@lists.osuosl.org \
--cc=karol.kolacinski@intel.com \
--cc=milena.olech@intel.com \
--cc=netdev@vger.kernel.org \
--cc=przemyslaw.kitszel@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.