* [PULL 01/54] qemu/compiler: Absorb 'clang-tsa.h'
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 02/54] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Philippe Mathieu-Daudé
` (53 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
We already have "qemu/compiler.h" for compiler-specific arrangements,
automatically included by "qemu/osdep.h" for each source file. No
need to explicitly include a header for a Clang particularity.
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250117170201.91182-1-philmd@linaro.org>
---
bsd-user/qemu.h | 1 -
include/block/block_int-common.h | 1 -
include/block/graph-lock.h | 2 -
include/exec/page-protection.h | 2 -
include/qemu/clang-tsa.h | 114 -------------------------------
include/qemu/compiler.h | 96 ++++++++++++++++++++++++++
include/qemu/thread.h | 1 -
block/create.c | 1 -
tests/unit/test-bdrv-drain.c | 1 -
tests/unit/test-block-iothread.c | 1 -
util/qemu-thread-posix.c | 1 -
11 files changed, 96 insertions(+), 125 deletions(-)
delete mode 100644 include/qemu/clang-tsa.h
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index 3eaa14f3f56..4e97c796318 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -40,7 +40,6 @@ extern char **environ;
#include "target.h"
#include "exec/gdbstub.h"
#include "exec/page-protection.h"
-#include "qemu/clang-tsa.h"
#include "accel/tcg/vcpu-state.h"
#include "qemu-os.h"
diff --git a/include/block/block_int-common.h b/include/block/block_int-common.h
index bb91a0f62fa..ebb4e56a503 100644
--- a/include/block/block_int-common.h
+++ b/include/block/block_int-common.h
@@ -28,7 +28,6 @@
#include "block/block-common.h"
#include "block/block-global-state.h"
#include "block/snapshot.h"
-#include "qemu/clang-tsa.h"
#include "qemu/iov.h"
#include "qemu/rcu.h"
#include "qemu/stats64.h"
diff --git a/include/block/graph-lock.h b/include/block/graph-lock.h
index dc8d9491843..2c26c721081 100644
--- a/include/block/graph-lock.h
+++ b/include/block/graph-lock.h
@@ -20,8 +20,6 @@
#ifndef GRAPH_LOCK_H
#define GRAPH_LOCK_H
-#include "qemu/clang-tsa.h"
-
/**
* Graph Lock API
* This API provides a rwlock used to protect block layer
diff --git a/include/exec/page-protection.h b/include/exec/page-protection.h
index bae3355f62c..3e0a8a03331 100644
--- a/include/exec/page-protection.h
+++ b/include/exec/page-protection.h
@@ -40,8 +40,6 @@
#ifdef CONFIG_USER_ONLY
-#include "qemu/clang-tsa.h"
-
void TSA_NO_TSA mmap_lock(void);
void TSA_NO_TSA mmap_unlock(void);
bool have_mmap_lock(void);
diff --git a/include/qemu/clang-tsa.h b/include/qemu/clang-tsa.h
deleted file mode 100644
index ba06fb8c924..00000000000
--- a/include/qemu/clang-tsa.h
+++ /dev/null
@@ -1,114 +0,0 @@
-#ifndef CLANG_TSA_H
-#define CLANG_TSA_H
-
-/*
- * Copyright 2018 Jarkko Hietaniemi <jhi@iki.fi>
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without
- * limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/* http://clang.llvm.org/docs/ThreadSafetyAnalysis.html
- *
- * TSA is available since clang 3.6-ish.
- */
-#ifdef __clang__
-# define TSA(x) __attribute__((x))
-#else
-# define TSA(x) /* No TSA, make TSA attributes no-ops. */
-#endif
-
-/* TSA_CAPABILITY() is used to annotate typedefs:
- *
- * typedef pthread_mutex_t TSA_CAPABILITY("mutex") tsa_mutex;
- */
-#define TSA_CAPABILITY(x) TSA(capability(x))
-
-/* TSA_GUARDED_BY() is used to annotate global variables,
- * the data is guarded:
- *
- * Foo foo TSA_GUARDED_BY(mutex);
- */
-#define TSA_GUARDED_BY(x) TSA(guarded_by(x))
-
-/* TSA_PT_GUARDED_BY() is used to annotate global pointers, the data
- * behind the pointer is guarded.
- *
- * Foo* ptr TSA_PT_GUARDED_BY(mutex);
- */
-#define TSA_PT_GUARDED_BY(x) TSA(pt_guarded_by(x))
-
-/* The TSA_REQUIRES() is used to annotate functions: the caller of the
- * function MUST hold the resource, the function will NOT release it.
- *
- * More than one mutex may be specified, comma-separated.
- *
- * void Foo(void) TSA_REQUIRES(mutex);
- */
-#define TSA_REQUIRES(...) TSA(requires_capability(__VA_ARGS__))
-#define TSA_REQUIRES_SHARED(...) TSA(requires_shared_capability(__VA_ARGS__))
-
-/* TSA_EXCLUDES() is used to annotate functions: the caller of the
- * function MUST NOT hold resource, the function first acquires the
- * resource, and then releases it.
- *
- * More than one mutex may be specified, comma-separated.
- *
- * void Foo(void) TSA_EXCLUDES(mutex);
- */
-#define TSA_EXCLUDES(...) TSA(locks_excluded(__VA_ARGS__))
-
-/* TSA_ACQUIRE() is used to annotate functions: the caller of the
- * function MUST NOT hold the resource, the function will acquire the
- * resource, but NOT release it.
- *
- * More than one mutex may be specified, comma-separated.
- *
- * void Foo(void) TSA_ACQUIRE(mutex);
- */
-#define TSA_ACQUIRE(...) TSA(acquire_capability(__VA_ARGS__))
-#define TSA_ACQUIRE_SHARED(...) TSA(acquire_shared_capability(__VA_ARGS__))
-
-/* TSA_RELEASE() is used to annotate functions: the caller of the
- * function MUST hold the resource, but the function will then release it.
- *
- * More than one mutex may be specified, comma-separated.
- *
- * void Foo(void) TSA_RELEASE(mutex);
- */
-#define TSA_RELEASE(...) TSA(release_capability(__VA_ARGS__))
-#define TSA_RELEASE_SHARED(...) TSA(release_shared_capability(__VA_ARGS__))
-
-/* TSA_NO_TSA is used to annotate functions. Use only when you need to.
- *
- * void Foo(void) TSA_NO_TSA;
- */
-#define TSA_NO_TSA TSA(no_thread_safety_analysis)
-
-/*
- * TSA_ASSERT() is used to annotate functions: This function will assert that
- * the lock is held. When it returns, the caller of the function is assumed to
- * already hold the resource.
- *
- * More than one mutex may be specified, comma-separated.
- */
-#define TSA_ASSERT(...) TSA(assert_capability(__VA_ARGS__))
-#define TSA_ASSERT_SHARED(...) TSA(assert_shared_capability(__VA_ARGS__))
-
-#endif /* #ifndef CLANG_TSA_H */
diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h
index d904408e5ed..496dac5ac11 100644
--- a/include/qemu/compiler.h
+++ b/include/qemu/compiler.h
@@ -207,6 +207,102 @@
# define QEMU_USED
#endif
+/*
+ * http://clang.llvm.org/docs/ThreadSafetyAnalysis.html
+ *
+ * TSA is available since clang 3.6-ish.
+ */
+#ifdef __clang__
+# define TSA(x) __attribute__((x))
+#else
+# define TSA(x) /* No TSA, make TSA attributes no-ops. */
+#endif
+
+/*
+ * TSA_CAPABILITY() is used to annotate typedefs:
+ *
+ * typedef pthread_mutex_t TSA_CAPABILITY("mutex") tsa_mutex;
+ */
+#define TSA_CAPABILITY(x) TSA(capability(x))
+
+/*
+ * TSA_GUARDED_BY() is used to annotate global variables,
+ * the data is guarded:
+ *
+ * Foo foo TSA_GUARDED_BY(mutex);
+ */
+#define TSA_GUARDED_BY(x) TSA(guarded_by(x))
+
+/*
+ * TSA_PT_GUARDED_BY() is used to annotate global pointers, the data
+ * behind the pointer is guarded.
+ *
+ * Foo* ptr TSA_PT_GUARDED_BY(mutex);
+ */
+#define TSA_PT_GUARDED_BY(x) TSA(pt_guarded_by(x))
+
+/*
+ * The TSA_REQUIRES() is used to annotate functions: the caller of the
+ * function MUST hold the resource, the function will NOT release it.
+ *
+ * More than one mutex may be specified, comma-separated.
+ *
+ * void Foo(void) TSA_REQUIRES(mutex);
+ */
+#define TSA_REQUIRES(...) TSA(requires_capability(__VA_ARGS__))
+#define TSA_REQUIRES_SHARED(...) TSA(requires_shared_capability(__VA_ARGS__))
+
+/*
+ * TSA_EXCLUDES() is used to annotate functions: the caller of the
+ * function MUST NOT hold resource, the function first acquires the
+ * resource, and then releases it.
+ *
+ * More than one mutex may be specified, comma-separated.
+ *
+ * void Foo(void) TSA_EXCLUDES(mutex);
+ */
+#define TSA_EXCLUDES(...) TSA(locks_excluded(__VA_ARGS__))
+
+/*
+ * TSA_ACQUIRE() is used to annotate functions: the caller of the
+ * function MUST NOT hold the resource, the function will acquire the
+ * resource, but NOT release it.
+ *
+ * More than one mutex may be specified, comma-separated.
+ *
+ * void Foo(void) TSA_ACQUIRE(mutex);
+ */
+#define TSA_ACQUIRE(...) TSA(acquire_capability(__VA_ARGS__))
+#define TSA_ACQUIRE_SHARED(...) TSA(acquire_shared_capability(__VA_ARGS__))
+
+/*
+ * TSA_RELEASE() is used to annotate functions: the caller of the
+ * function MUST hold the resource, but the function will then release it.
+ *
+ * More than one mutex may be specified, comma-separated.
+ *
+ * void Foo(void) TSA_RELEASE(mutex);
+ */
+#define TSA_RELEASE(...) TSA(release_capability(__VA_ARGS__))
+#define TSA_RELEASE_SHARED(...) TSA(release_shared_capability(__VA_ARGS__))
+
+/*
+ * TSA_NO_TSA is used to annotate functions. Use only when you need to.
+ *
+ * void Foo(void) TSA_NO_TSA;
+ */
+#define TSA_NO_TSA TSA(no_thread_safety_analysis)
+
+/*
+ * TSA_ASSERT() is used to annotate functions: This function will assert that
+ * the lock is held. When it returns, the caller of the function is assumed to
+ * already hold the resource.
+ *
+ * More than one mutex may be specified, comma-separated.
+ */
+#define TSA_ASSERT(...) TSA(assert_capability(__VA_ARGS__))
+#define TSA_ASSERT_SHARED(...) TSA(assert_shared_capability(__VA_ARGS__))
+
/*
* Ugly CPP trick that is like "defined FOO", but also works in C
* code. Useful to replace #ifdef with "if" statements; assumes
diff --git a/include/qemu/thread.h b/include/qemu/thread.h
index 7eba27a7049..6f800aad31a 100644
--- a/include/qemu/thread.h
+++ b/include/qemu/thread.h
@@ -3,7 +3,6 @@
#include "qemu/processor.h"
#include "qemu/atomic.h"
-#include "qemu/clang-tsa.h"
typedef struct QemuCond QemuCond;
typedef struct QemuSemaphore QemuSemaphore;
diff --git a/block/create.c b/block/create.c
index 72abafb4c12..6b23a216753 100644
--- a/block/create.c
+++ b/block/create.c
@@ -24,7 +24,6 @@
#include "qemu/osdep.h"
#include "block/block_int.h"
-#include "qemu/clang-tsa.h"
#include "qemu/job.h"
#include "qemu/main-loop.h"
#include "qapi/qapi-commands-block-core.h"
diff --git a/tests/unit/test-bdrv-drain.c b/tests/unit/test-bdrv-drain.c
index 98ad89b390c..7410e6f3528 100644
--- a/tests/unit/test-bdrv-drain.c
+++ b/tests/unit/test-bdrv-drain.c
@@ -28,7 +28,6 @@
#include "system/block-backend.h"
#include "qapi/error.h"
#include "qemu/main-loop.h"
-#include "qemu/clang-tsa.h"
#include "iothread.h"
static QemuEvent done_event;
diff --git a/tests/unit/test-block-iothread.c b/tests/unit/test-block-iothread.c
index 7324ea4a68d..2b358eaaa82 100644
--- a/tests/unit/test-block-iothread.c
+++ b/tests/unit/test-block-iothread.c
@@ -29,7 +29,6 @@
#include "system/block-backend.h"
#include "qapi/error.h"
#include "qobject/qdict.h"
-#include "qemu/clang-tsa.h"
#include "qemu/main-loop.h"
#include "iothread.h"
diff --git a/util/qemu-thread-posix.c b/util/qemu-thread-posix.c
index 6fff4162ac6..b2e26e21205 100644
--- a/util/qemu-thread-posix.c
+++ b/util/qemu-thread-posix.c
@@ -17,7 +17,6 @@
#include "qemu-thread-common.h"
#include "qemu/tsan.h"
#include "qemu/bitmap.h"
-#include "qemu/clang-tsa.h"
#ifdef CONFIG_PTHREAD_SET_NAME_NP
#include <pthread_np.h>
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 02/54] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 01/54] qemu/compiler: Absorb 'clang-tsa.h' Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 03/54] gdbstub: Check for TCG before calling tb_flush() Philippe Mathieu-Daudé
` (52 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
Both CPUClass::gdb_read_register() and CPUClass::gdb_write_register()
handlers are called from common gdbstub code, and won't be called with
register index over CPUClass::gdb_num_core_regs:
int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (reg < cc->gdb_num_core_regs) {
return cc->gdb_read_register(cpu, buf, reg);
}
...
}
static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (reg < cc->gdb_num_core_regs) {
return cc->gdb_write_register(cpu, mem_buf, reg);
}
...
}
Clarify that in CPUClass docstring, and remove unreachable code on
the microblaze and openrisc implementations.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20250122093028.52416-3-philmd@linaro.org>
---
include/hw/core/cpu.h | 2 ++
target/microblaze/gdbstub.c | 5 -----
target/openrisc/gdbstub.c | 5 -----
3 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index fb397cdfc53..7b6b22c431b 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -124,7 +124,9 @@ struct SysemuCPUOps;
* @get_pc: Callback for getting the Program Counter register.
* As above, with the semantics of the target architecture.
* @gdb_read_register: Callback for letting GDB read a register.
+ * No more than @gdb_num_core_regs registers can be read.
* @gdb_write_register: Callback for letting GDB write a register.
+ * No more than @gdb_num_core_regs registers can be written.
* @gdb_adjust_breakpoint: Callback for adjusting the address of a
* breakpoint. Used by AVR to handle a gdb mis-feature with
* its Harvard architecture split code and data.
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 09d74e164d0..d493681d38d 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -110,14 +110,9 @@ int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n)
int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- CPUClass *cc = CPU_GET_CLASS(cs);
CPUMBState *env = cpu_env(cs);
uint32_t tmp;
- if (n > cc->gdb_num_core_regs) {
- return 0;
- }
-
tmp = ldl_p(mem_buf);
switch (n) {
diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c
index c2a77d5d4d5..45bba80d878 100644
--- a/target/openrisc/gdbstub.c
+++ b/target/openrisc/gdbstub.c
@@ -47,14 +47,9 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- CPUClass *cc = CPU_GET_CLASS(cs);
CPUOpenRISCState *env = cpu_env(cs);
uint32_t tmp;
- if (n > cc->gdb_num_core_regs) {
- return 0;
- }
-
tmp = ldl_p(mem_buf);
if (n < 32) {
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 03/54] gdbstub: Check for TCG before calling tb_flush()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 01/54] qemu/compiler: Absorb 'clang-tsa.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 02/54] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 04/54] cpus: Cache CPUClass early in instance_init() handler Philippe Mathieu-Daudé
` (51 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
Use the tcg_enabled() check so the compiler can elide
the call when TCG isn't available, allowing to remove
the tb_flush() stub.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-4-philmd@linaro.org>
---
accel/stubs/tcg-stub.c | 4 ----
gdbstub/system.c | 5 ++++-
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
index 7f4208fddf2..b2b9881bdfb 100644
--- a/accel/stubs/tcg-stub.c
+++ b/accel/stubs/tcg-stub.c
@@ -14,10 +14,6 @@
#include "exec/tb-flush.h"
#include "exec/exec-all.h"
-void tb_flush(CPUState *cpu)
-{
-}
-
G_NORETURN void cpu_loop_exit(CPUState *cpu)
{
g_assert_not_reached();
diff --git a/gdbstub/system.c b/gdbstub/system.c
index 8ce79fa88cf..7f047a285c8 100644
--- a/gdbstub/system.c
+++ b/gdbstub/system.c
@@ -22,6 +22,7 @@
#include "system/cpus.h"
#include "system/runstate.h"
#include "system/replay.h"
+#include "system/tcg.h"
#include "hw/core/cpu.h"
#include "hw/cpu/cluster.h"
#include "hw/boards.h"
@@ -171,7 +172,9 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state)
} else {
trace_gdbstub_hit_break();
}
- tb_flush(cpu);
+ if (tcg_enabled()) {
+ tb_flush(cpu);
+ }
ret = GDB_SIGNAL_TRAP;
break;
case RUN_STATE_PAUSED:
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 04/54] cpus: Cache CPUClass early in instance_init() handler
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-03-06 15:46 ` [PULL 03/54] gdbstub: Check for TCG before calling tb_flush() Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 05/54] cpus: Keep default fields initialization in cpu_common_initfn() Philippe Mathieu-Daudé
` (50 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
Cache CPUClass as early as possible, when the instance
is initialized.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-5-philmd@linaro.org>
---
cpu-target.c | 3 ---
hw/core/cpu-common.c | 3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index 667688332c9..89874496a41 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -134,9 +134,6 @@ const VMStateDescription vmstate_cpu_common = {
bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
- /* cache the cpu class for the hotpath */
- cpu->cc = CPU_GET_CLASS(cpu);
-
if (!accel_cpu_common_realize(cpu, errp)) {
return false;
}
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index cb79566cc51..ff605059c15 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -238,6 +238,9 @@ static void cpu_common_initfn(Object *obj)
{
CPUState *cpu = CPU(obj);
+ /* cache the cpu class for the hotpath */
+ cpu->cc = CPU_GET_CLASS(cpu);
+
gdb_init_cpu(cpu);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 05/54] cpus: Keep default fields initialization in cpu_common_initfn()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2025-03-06 15:46 ` [PULL 04/54] cpus: Cache CPUClass early in instance_init() handler Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 06/54] accel/accel: Make TYPE_ACCEL abstract Philippe Mathieu-Daudé
` (49 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
cpu_common_initfn() is our target agnostic initializer,
while cpu_exec_initfn() is the target specific one.
The %as and %num_ases fields are not target specific,
so initialize them in the common helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-6-philmd@linaro.org>
---
cpu-target.c | 3 ---
hw/core/cpu-common.c | 2 ++
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index 89874496a41..75501a909df 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -234,9 +234,6 @@ void cpu_class_init_props(DeviceClass *dc)
void cpu_exec_initfn(CPUState *cpu)
{
- cpu->as = NULL;
- cpu->num_ases = 0;
-
#ifndef CONFIG_USER_ONLY
cpu->memory = get_system_memory();
object_ref(OBJECT(cpu->memory));
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index ff605059c15..71425cb7422 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -244,6 +244,8 @@ static void cpu_common_initfn(Object *obj)
gdb_init_cpu(cpu);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
+ cpu->as = NULL;
+ cpu->num_ases = 0;
/* user-mode doesn't have configurable SMP topology */
/* the default value is changed by qemu_init_vcpu() for system-mode */
cpu->nr_threads = 1;
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 06/54] accel/accel: Make TYPE_ACCEL abstract
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2025-03-06 15:46 ` [PULL 05/54] cpus: Keep default fields initialization in cpu_common_initfn() Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 07/54] accel/tcg: Remove pointless initialization of cflags_next_tb Philippe Mathieu-Daudé
` (48 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@redhat.com>
There is no generic acceleration, we have to use specific
implementations. Make the base class abstract.
Fixes: b14a0b7469fa ("accel: Use QOM classes for accel types")
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <20200129212345.20547-3-philmd@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
accel/accel-target.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/accel/accel-target.c b/accel/accel-target.c
index 08626c00c2d..3236d6335b1 100644
--- a/accel/accel-target.c
+++ b/accel/accel-target.c
@@ -38,6 +38,7 @@ static const TypeInfo accel_type = {
.parent = TYPE_OBJECT,
.class_size = sizeof(AccelClass),
.instance_size = sizeof(AccelState),
+ .abstract = true,
};
/* Lookup AccelClass from opt_name. Returns NULL if not found */
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 07/54] accel/tcg: Remove pointless initialization of cflags_next_tb
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2025-03-06 15:46 ` [PULL 06/54] accel/accel: Make TYPE_ACCEL abstract Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 08/54] accel/tcg: Build tcg_flags helpers as common code Philippe Mathieu-Daudé
` (47 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
cflags_next_tb is always re-initialized in the CPU Reset()
handler in cpu_common_reset_hold(), no need to initialize
it in cpu_common_initfn().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240427155714.53669-13-philmd@linaro.org>
---
hw/core/cpu-common.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index 71425cb7422..d5cd227fe6d 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -249,7 +249,6 @@ static void cpu_common_initfn(Object *obj)
/* user-mode doesn't have configurable SMP topology */
/* the default value is changed by qemu_init_vcpu() for system-mode */
cpu->nr_threads = 1;
- cpu->cflags_next_tb = -1;
/* allocate storage for thread info, initialise condition variables */
cpu->thread = g_new0(QemuThread, 1);
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 08/54] accel/tcg: Build tcg_flags helpers as common code
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2025-03-06 15:46 ` [PULL 07/54] accel/tcg: Remove pointless initialization of cflags_next_tb Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 09/54] accel/tcg: Restrict tlb_init() / destroy() to TCG Philippe Mathieu-Daudé
` (46 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
While cpu-exec.c is build for each target,tcg_flags helpers
aren't target specific. Move them to cpu-exec-common.c to
build them once.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-8-philmd@linaro.org>
---
accel/tcg/cpu-exec-common.c | 33 +++++++++++++++++++++++++++++++++
accel/tcg/cpu-exec.c | 32 --------------------------------
2 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c
index 6ecfc4e7c21..100746d555a 100644
--- a/accel/tcg/cpu-exec-common.c
+++ b/accel/tcg/cpu-exec-common.c
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
+#include "exec/log.h"
#include "system/cpus.h"
#include "system/tcg.h"
#include "qemu/plugin.h"
@@ -25,6 +26,38 @@
bool tcg_allowed;
+bool tcg_cflags_has(CPUState *cpu, uint32_t flags)
+{
+ return cpu->tcg_cflags & flags;
+}
+
+void tcg_cflags_set(CPUState *cpu, uint32_t flags)
+{
+ cpu->tcg_cflags |= flags;
+}
+
+uint32_t curr_cflags(CPUState *cpu)
+{
+ uint32_t cflags = cpu->tcg_cflags;
+
+ /*
+ * Record gdb single-step. We should be exiting the TB by raising
+ * EXCP_DEBUG, but to simplify other tests, disable chaining too.
+ *
+ * For singlestep and -d nochain, suppress goto_tb so that
+ * we can log -d cpu,exec after every TB.
+ */
+ if (unlikely(cpu->singlestep_enabled)) {
+ cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1;
+ } else if (qatomic_read(&one_insn_per_tb)) {
+ cflags |= CF_NO_GOTO_TB | 1;
+ } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
+ cflags |= CF_NO_GOTO_TB;
+ }
+
+ return cflags;
+}
+
/* exit the current TB, but without causing any exception to be raised */
void cpu_loop_exit_noexc(CPUState *cpu)
{
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 8b773d88478..be2ba199d3d 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -148,38 +148,6 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
}
#endif /* CONFIG USER ONLY */
-bool tcg_cflags_has(CPUState *cpu, uint32_t flags)
-{
- return cpu->tcg_cflags & flags;
-}
-
-void tcg_cflags_set(CPUState *cpu, uint32_t flags)
-{
- cpu->tcg_cflags |= flags;
-}
-
-uint32_t curr_cflags(CPUState *cpu)
-{
- uint32_t cflags = cpu->tcg_cflags;
-
- /*
- * Record gdb single-step. We should be exiting the TB by raising
- * EXCP_DEBUG, but to simplify other tests, disable chaining too.
- *
- * For singlestep and -d nochain, suppress goto_tb so that
- * we can log -d cpu,exec after every TB.
- */
- if (unlikely(cpu->singlestep_enabled)) {
- cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1;
- } else if (qatomic_read(&one_insn_per_tb)) {
- cflags |= CF_NO_GOTO_TB | 1;
- } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
- cflags |= CF_NO_GOTO_TB;
- }
-
- return cflags;
-}
-
struct tb_desc {
vaddr pc;
uint64_t cs_base;
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 09/54] accel/tcg: Restrict tlb_init() / destroy() to TCG
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2025-03-06 15:46 ` [PULL 08/54] accel/tcg: Build tcg_flags helpers as common code Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 10/54] accel/tcg: Restrict 'icount_align_option' global " Philippe Mathieu-Daudé
` (45 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
Move CPU TLB related methods to accel/tcg/ scope,
in "internal-common.h".
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-9-philmd@linaro.org>
---
accel/tcg/internal-common.h | 11 +++++++++++
include/exec/exec-all.h | 16 ----------------
accel/tcg/user-exec-stub.c | 11 +++++++++++
3 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
index c8d714256cb..d3186721839 100644
--- a/accel/tcg/internal-common.h
+++ b/accel/tcg/internal-common.h
@@ -53,6 +53,17 @@ TranslationBlock *tb_link_page(TranslationBlock *tb);
void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
uintptr_t host_pc);
+/**
+ * tlb_init - initialize a CPU's TLB
+ * @cpu: CPU whose TLB should be initialized
+ */
+void tlb_init(CPUState *cpu);
+/**
+ * tlb_destroy - destroy a CPU's TLB
+ * @cpu: CPU whose TLB should be destroyed
+ */
+void tlb_destroy(CPUState *cpu);
+
bool tcg_exec_realizefn(CPUState *cpu, Error **errp);
void tcg_exec_unrealizefn(CPUState *cpu);
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index d9045c9ac4c..8eb0df48f94 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -29,16 +29,6 @@
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* cputlb.c */
-/**
- * tlb_init - initialize a CPU's TLB
- * @cpu: CPU whose TLB should be initialized
- */
-void tlb_init(CPUState *cpu);
-/**
- * tlb_destroy - destroy a CPU's TLB
- * @cpu: CPU whose TLB should be destroyed
- */
-void tlb_destroy(CPUState *cpu);
/**
* tlb_flush_page:
* @cpu: CPU whose TLB should be flushed
@@ -223,12 +213,6 @@ void tlb_set_page(CPUState *cpu, vaddr addr,
hwaddr paddr, int prot,
int mmu_idx, vaddr size);
#else
-static inline void tlb_init(CPUState *cpu)
-{
-}
-static inline void tlb_destroy(CPUState *cpu)
-{
-}
static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
{
}
diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c
index 4fbe2dbdc88..1d52f48226a 100644
--- a/accel/tcg/user-exec-stub.c
+++ b/accel/tcg/user-exec-stub.c
@@ -1,6 +1,7 @@
#include "qemu/osdep.h"
#include "hw/core/cpu.h"
#include "exec/replay-core.h"
+#include "internal-common.h"
void cpu_resume(CPUState *cpu)
{
@@ -18,6 +19,16 @@ void cpu_exec_reset_hold(CPUState *cpu)
{
}
+/* User mode emulation does not support softmmu yet. */
+
+void tlb_init(CPUState *cpu)
+{
+}
+
+void tlb_destroy(CPUState *cpu)
+{
+}
+
/* User mode emulation does not support record/replay yet. */
bool replay_exception(void)
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 10/54] accel/tcg: Restrict 'icount_align_option' global to TCG
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2025-03-06 15:46 ` [PULL 09/54] accel/tcg: Restrict tlb_init() / destroy() to TCG Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 11/54] accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' Philippe Mathieu-Daudé
` (44 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
Since commit 740b1759734 ("cpu-timers, icount: new modules")
we don't need to expose icount_align_option to all the
system code, we can restrict it to TCG. Since it is used as
a boolean, declare it as 'bool' type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-10-philmd@linaro.org>
---
accel/tcg/internal-common.h | 2 ++
include/system/cpus.h | 2 --
accel/tcg/icount-common.c | 2 ++
system/globals.c | 1 -
4 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
index d3186721839..7ef620d9631 100644
--- a/accel/tcg/internal-common.h
+++ b/accel/tcg/internal-common.h
@@ -17,6 +17,8 @@ extern int64_t max_advance;
extern bool one_insn_per_tb;
+extern bool icount_align_option;
+
/*
* Return true if CS is not running in parallel with other cpus, either
* because there are no other cpus or we are within an exclusive context.
diff --git a/include/system/cpus.h b/include/system/cpus.h
index 3d8fd368f32..1cffeaaf5c4 100644
--- a/include/system/cpus.h
+++ b/include/system/cpus.h
@@ -38,8 +38,6 @@ void resume_all_vcpus(void);
void pause_all_vcpus(void);
void cpu_stop_current(void);
-extern int icount_align_option;
-
/* Unblock cpu */
void qemu_cpu_kick_self(void);
diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c
index b178dccec45..402d3e3f4e8 100644
--- a/accel/tcg/icount-common.c
+++ b/accel/tcg/icount-common.c
@@ -48,6 +48,8 @@ static bool icount_sleep = true;
/* Arbitrarily pick 1MIPS as the minimum allowable speed. */
#define MAX_ICOUNT_SHIFT 10
+bool icount_align_option;
+
/* Do not count executed instructions */
ICountMode use_icount = ICOUNT_DISABLED;
diff --git a/system/globals.c b/system/globals.c
index 316623bd20a..9640c9511e9 100644
--- a/system/globals.c
+++ b/system/globals.c
@@ -58,7 +58,6 @@ unsigned int nb_prom_envs;
const char *prom_envs[MAX_PROM_ENVS];
uint8_t *boot_splash_filedata;
int only_migratable; /* turn it off unless user states otherwise */
-int icount_align_option;
/* The bytes in qemu_uuid are in the order specified by RFC4122, _not_ in the
* little-endian "wire format" described in the SMBIOS 2.6 specification.
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 11/54] accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h'
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2025-03-06 15:46 ` [PULL 10/54] accel/tcg: Restrict 'icount_align_option' global " Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 12/54] accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h' Philippe Mathieu-Daudé
` (43 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
TCGCPUOps structure makes more sense in the accelerator context
rather than hardware emulation. Move it under the accel/tcg/ scope.
Mechanical change doing:
$ sed -i -e 's,hw/core/tcg-cpu-ops.h,accel/tcg/cpu-ops.h,g' \
$(git grep -l hw/core/tcg-cpu-ops.h)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-11-philmd@linaro.org>
---
MAINTAINERS | 2 +-
include/{hw/core/tcg-cpu-ops.h => accel/tcg/cpu-ops.h} | 0
accel/tcg/cpu-exec.c | 2 +-
accel/tcg/cputlb.c | 2 +-
accel/tcg/translate-all.c | 2 +-
accel/tcg/user-exec.c | 2 +-
accel/tcg/watchpoint.c | 2 +-
bsd-user/signal.c | 2 +-
hw/mips/jazz.c | 2 +-
linux-user/signal.c | 2 +-
system/physmem.c | 2 +-
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/arm/tcg/cpu-v7m.c | 2 +-
target/arm/tcg/cpu32.c | 2 +-
target/arm/tcg/mte_helper.c | 2 +-
target/arm/tcg/sve_helper.c | 2 +-
target/avr/cpu.c | 2 +-
target/avr/helper.c | 2 +-
target/hexagon/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/loongarch/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/ppc/cpu_init.c | 2 +-
target/riscv/cpu_helper.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/s390x/tcg/mem_helper.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
37 files changed, 36 insertions(+), 36 deletions(-)
rename include/{hw/core/tcg-cpu-ops.h => accel/tcg/cpu-ops.h} (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 692628cd780..2d9ba810851 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -175,7 +175,7 @@ F: include/exec/helper-info.c.inc
F: include/exec/page-protection.h
F: include/system/cpus.h
F: include/system/tcg.h
-F: include/hw/core/tcg-cpu-ops.h
+F: include/accel/tcg/cpu-ops.h
F: host/include/*/host/cpuinfo.h
F: util/cpuinfo-*.c
F: include/tcg/
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/accel/tcg/cpu-ops.h
similarity index 100%
rename from include/hw/core/tcg-cpu-ops.h
rename to include/accel/tcg/cpu-ops.h
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index be2ba199d3d..3a3c45f52ed 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -22,7 +22,7 @@
#include "qapi/error.h"
#include "qapi/type-helpers.h"
#include "hw/core/cpu.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "trace.h"
#include "disas/disas.h"
#include "exec/cpu-common.h"
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index ad158050a13..c8761683a0a 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -19,7 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/memory.h"
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index d4189c73860..786e2f6f1a7 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -58,7 +58,7 @@
#include "system/cpu-timers.h"
#include "system/tcg.h"
#include "qapi/error.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "tb-jmp-cache.h"
#include "tb-hash.h"
#include "tb-context.h"
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 0561c4f6dc7..c4454100ad7 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -17,7 +17,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
index af57d182d5b..40112b2b2e7 100644
--- a/accel/tcg/watchpoint.c
+++ b/accel/tcg/watchpoint.c
@@ -26,7 +26,7 @@
#include "tb-internal.h"
#include "system/tcg.h"
#include "system/replay.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "hw/core/cpu.h"
#include "internal-common.h"
diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index ff2ccbbf605..ab1d9ddd50f 100644
--- a/bsd-user/signal.c
+++ b/bsd-user/signal.c
@@ -29,7 +29,7 @@
#include "gdbstub/user.h"
#include "signal-common.h"
#include "trace.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "host-signal.h"
/* target_siginfo_t must fit in gdbstub's siginfo save area. */
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index c89610639a9..1700c3765de 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -50,7 +50,7 @@
#include "qemu/error-report.h"
#include "qemu/help_option.h"
#ifdef CONFIG_TCG
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#endif /* CONFIG_TCG */
#include "cpu.h"
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 81a98c6d02f..4799b79dede 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -21,7 +21,7 @@
#include "qemu/cutils.h"
#include "gdbstub/user.h"
#include "exec/page-protection.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include <sys/ucontext.h>
#include <sys/resource.h>
diff --git a/system/physmem.c b/system/physmem.c
index eff8b55c2dd..8c1736f84ee 100644
--- a/system/physmem.c
+++ b/system/physmem.c
@@ -28,7 +28,7 @@
#include "qemu/lockable.h"
#ifdef CONFIG_TCG
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#endif /* CONFIG_TCG */
#include "exec/exec-all.h"
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index f5dd7449876..57e41fcd784 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -227,7 +227,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
};
#endif
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 656070afb59..ac1ceec2110 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -29,7 +29,7 @@
#include "cpu.h"
#ifdef CONFIG_TCG
#include "exec/translation-block.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#endif /* CONFIG_TCG */
#include "internals.h"
#include "cpu-features.h"
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 03acdf83e00..29a41fde694 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -10,7 +10,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "internals.h"
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 0f1c5bc87e8..2c45b7eddda 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -10,7 +10,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "internals.h"
#include "target/arm/idau.h"
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index f72ce2ae0d4..5d6d8a17ae8 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -31,7 +31,7 @@
#endif
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "qapi/error.h"
#include "qemu/guest-random.h"
#include "mte_helper.h"
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index c206ca65ceb..d786b4b1118 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -28,7 +28,7 @@
#include "tcg/tcg.h"
#include "vec_internal.h"
#include "sve_ldst_internal.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#ifdef CONFIG_USER_ONLY
#include "user/page-protection.h"
#endif
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 8a126ff3222..5a0e21465e5 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -203,7 +203,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
.get_phys_page_debug = avr_cpu_get_phys_page_debug,
};
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps avr_tcg_ops = {
.initialize = avr_cpu_tcg_init,
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 345708a1b39..9ea6870e44d 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -22,7 +22,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "cpu.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 0b7fc98f6ce..238e63bcea4 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -321,7 +321,7 @@ static void hexagon_cpu_init(Object *obj)
{
}
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init,
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 5655677431c..4bb5cff624e 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -245,7 +245,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
};
#endif
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hppa_tcg_ops = {
.initialize = hppa_translate_init,
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 14ee038079a..f09ee813ac9 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -105,7 +105,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
}
#endif
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps x86_tcg_ops = {
.initialize = tcg_x86_init,
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ac514a15fba..b4b82425b18 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -857,7 +857,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
#ifdef CONFIG_TCG
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps loongarch_tcg_ops = {
.initialize = loongarch_translate_init,
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 2617d8f6ede..eedda07c2ab 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -582,7 +582,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
};
#endif /* !CONFIG_USER_ONLY */
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps m68k_tcg_ops = {
.initialize = m68k_tcg_init,
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index f114789abd8..13d194cef88 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -419,7 +419,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
};
#endif
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mb_tcg_ops = {
.initialize = mb_tcg_init,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 47cd7cfdcef..0b267d2e507 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -544,7 +544,7 @@ static const Property mips_cpu_properties[] = {
};
#ifdef CONFIG_TCG
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mips_tcg_ops = {
.initialize = mips_tcg_init,
.translate_code = mips_translate_code,
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index b7bab0d7abf..0669ba2fd10 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -232,7 +232,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
};
#endif
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 062a6e85fba..425049ab093 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7430,7 +7430,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
#endif
#ifdef CONFIG_TCG
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 3f5fd861a80..34092f372df 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -27,7 +27,7 @@
#include "exec/page-protection.h"
#include "instmap.h"
#include "tcg/tcg-op.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "trace.h"
#include "semihosting/common-semi.h"
#include "system/cpu-timers.h"
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f1d971eec1f..70f4c7984aa 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -31,7 +31,7 @@
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "hw/core/accel-cpu.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "tcg/tcg.h"
#ifndef CONFIG_USER_ONLY
#include "hw/boards.h"
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 37a6fdd569b..7d5fcbf76ac 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -200,7 +200,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
};
#endif
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps rx_tcg_ops = {
.initialize = rx_translate_init,
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 97d41c23de7..3bea014f9ee 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -322,7 +322,7 @@ static const Property s390x_cpu_properties[] = {
#endif
#ifdef CONFIG_TCG
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index c6ab2901e5a..ea9fa64d6b4 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -28,7 +28,7 @@
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
#include "qemu/int128.h"
#include "qemu/atomic128.h"
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ccfe222bdf3..22cdf9b4e12 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -256,7 +256,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
};
#endif
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps superh_tcg_ops = {
.initialize = sh4_translate_init,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index fbd38ec334a..e3b46137178 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -992,7 +992,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
#endif
#ifdef CONFIG_TCG
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 95202fadbfd..eb794674c8d 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -168,7 +168,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
.get_phys_page_debug = tricore_cpu_get_phys_page_debug,
};
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps tricore_tcg_ops = {
.initialize = tricore_tcg_init,
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 4eb699d1f45..efbfe73fcfb 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -228,7 +228,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
};
#endif
-#include "hw/core/tcg-cpu-ops.h"
+#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps xtensa_tcg_ops = {
.initialize = xtensa_translate_init,
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 12/54] accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h'
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2025-03-06 15:46 ` [PULL 11/54] accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 13/54] accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h' Philippe Mathieu-Daudé
` (42 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
AccelCPUClass is for accelerator to initialize target specific
features of a vCPU. Not really related to hardware emulation,
rename "hw/core/accel-cpu.h" as "accel/accel-cpu-target.h"
(using the explicit -target suffix).
More importantly, target specific header often access the
target specific definitions which are in each target/FOO/cpu.h
header, usually included generically as "cpu.h" relative to
target/FOO/. However, there is already a "cpu.h" in hw/core/
which takes precedence. This change allows "accel-cpu-target.h"
to include a target "cpu.h".
Mechanical change doing:
$ git mv include/hw/core/accel-cpu.h \
include/accel/accel-cpu-target.h
$ sed -i -e 's,hw/core/accel-cpu.h,accel/accel-cpu-target.h,' \
$(git grep -l hw/core/accel-cpu.h)
and renaming header guard 'ACCEL_CPU_TARGET_H'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-12-philmd@linaro.org>
---
MAINTAINERS | 2 +-
include/{hw/core/accel-cpu.h => accel/accel-cpu-target.h} | 4 ++--
accel/accel-target.c | 2 +-
cpu-target.c | 2 +-
target/i386/hvf/hvf-cpu.c | 2 +-
target/i386/kvm/kvm-cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/ppc/kvm.c | 2 +-
target/riscv/kvm/kvm-cpu.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 2 +-
10 files changed, 11 insertions(+), 11 deletions(-)
rename include/{hw/core/accel-cpu.h => accel/accel-cpu-target.h} (95%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2d9ba810851..a0e462d03ca 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -499,7 +499,7 @@ R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: include/qemu/accel.h
F: include/system/accel-*.h
-F: include/hw/core/accel-cpu.h
+F: include/accel/accel-cpu-target.h
F: accel/accel-*.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
diff --git a/include/hw/core/accel-cpu.h b/include/accel/accel-cpu-target.h
similarity index 95%
rename from include/hw/core/accel-cpu.h
rename to include/accel/accel-cpu-target.h
index 24dad45ab9e..0a8e518600d 100644
--- a/include/hw/core/accel-cpu.h
+++ b/include/accel/accel-cpu-target.h
@@ -8,8 +8,8 @@
* See the COPYING file in the top-level directory.
*/
-#ifndef ACCEL_CPU_H
-#define ACCEL_CPU_H
+#ifndef ACCEL_CPU_TARGET_H
+#define ACCEL_CPU_TARGET_H
/*
* This header is used to define new accelerator-specific target-specific
diff --git a/accel/accel-target.c b/accel/accel-target.c
index 3236d6335b1..83587274626 100644
--- a/accel/accel-target.c
+++ b/accel/accel-target.c
@@ -27,7 +27,7 @@
#include "qemu/accel.h"
#include "cpu.h"
-#include "hw/core/accel-cpu.h"
+#include "accel/accel-cpu-target.h"
#ifndef CONFIG_USER_ONLY
#include "accel-system.h"
diff --git a/cpu-target.c b/cpu-target.c
index 75501a909df..f97f3a14751 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -44,7 +44,7 @@
#include "exec/tb-flush.h"
#include "exec/translation-block.h"
#include "exec/log.h"
-#include "hw/core/accel-cpu.h"
+#include "accel/accel-cpu-target.h"
#include "trace/trace-root.h"
#include "qemu/accel.h"
diff --git a/target/i386/hvf/hvf-cpu.c b/target/i386/hvf/hvf-cpu.c
index 560b5a05940..b5f4c80028f 100644
--- a/target/i386/hvf/hvf-cpu.c
+++ b/target/i386/hvf/hvf-cpu.c
@@ -14,7 +14,7 @@
#include "system/system.h"
#include "hw/boards.h"
#include "system/hvf.h"
-#include "hw/core/accel-cpu.h"
+#include "accel/accel-cpu-target.h"
#include "hvf-i386.h"
static void hvf_cpu_max_instance_init(X86CPU *cpu)
diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
index 1bda403f88b..6269fa80452 100644
--- a/target/i386/kvm/kvm-cpu.c
+++ b/target/i386/kvm/kvm-cpu.c
@@ -15,7 +15,7 @@
#include "hw/boards.h"
#include "kvm_i386.h"
-#include "hw/core/accel-cpu.h"
+#include "accel/accel-cpu-target.h"
static void kvm_set_guest_phys_bits(CPUState *cs)
{
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index f09ee813ac9..b8aff825eec 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "helper-tcg.h"
#include "qemu/accel.h"
-#include "hw/core/accel-cpu.h"
+#include "accel/accel-cpu-target.h"
#include "exec/translation-block.h"
#include "tcg-cpu.h"
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 966c2c65723..216638dee40 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -49,7 +49,7 @@
#include "elf.h"
#include "system/kvm_int.h"
#include "system/kvm.h"
-#include "hw/core/accel-cpu.h"
+#include "accel/accel-cpu-target.h"
#include CONFIG_DEVICES
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 7f3b59cb72c..4ffeeaa1c95 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -32,7 +32,7 @@
#include "system/kvm_int.h"
#include "cpu.h"
#include "trace.h"
-#include "hw/core/accel-cpu.h"
+#include "accel/accel-cpu-target.h"
#include "hw/pci/pci.h"
#include "exec/memattrs.h"
#include "exec/address-spaces.h"
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 70f4c7984aa..5aef9eef366 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -30,7 +30,7 @@
#include "qemu/accel.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
-#include "hw/core/accel-cpu.h"
+#include "accel/accel-cpu-target.h"
#include "accel/tcg/cpu-ops.h"
#include "tcg/tcg.h"
#ifndef CONFIG_USER_ONLY
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 13/54] accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h'
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2025-03-06 15:46 ` [PULL 12/54] accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h' Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 14/54] accel/accel-cpu-target.h: Include missing 'cpu.h' header Philippe Mathieu-Daudé
` (41 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
The heavily imported "system/cpus.h" header includes "accel-ops.h"
to get AccelOpsClass type declaration. Reduce headers pressure by
forward declaring it in "qemu/typedefs.h", where we already
declare the AccelCPUState type.
Reduce "system/cpus.h" inclusions by only including
"system/accel-ops.h" when necessary.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-14-philmd@linaro.org>
---
include/qemu/typedefs.h | 1 +
include/system/accel-ops.h | 1 -
include/system/cpus.h | 2 --
accel/accel-system.c | 1 +
accel/hvf/hvf-accel-ops.c | 1 +
accel/kvm/kvm-accel-ops.c | 1 +
accel/qtest/qtest.c | 1 +
accel/tcg/cpu-exec-common.c | 1 -
accel/tcg/cpu-exec.c | 1 -
accel/tcg/monitor.c | 1 -
accel/tcg/tcg-accel-ops.c | 1 +
accel/tcg/translate-all.c | 1 -
accel/xen/xen-all.c | 1 +
cpu-common.c | 1 -
cpu-target.c | 1 +
gdbstub/system.c | 1 +
system/cpus.c | 1 +
target/i386/nvmm/nvmm-accel-ops.c | 1 +
target/i386/whpx/whpx-accel-ops.c | 1 +
19 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 3d84efcac47..465cc501773 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -22,6 +22,7 @@
* Please keep this list in case-insensitive alphabetical order.
*/
typedef struct AccelCPUState AccelCPUState;
+typedef struct AccelOpsClass AccelOpsClass;
typedef struct AccelState AccelState;
typedef struct AddressSpace AddressSpace;
typedef struct AioContext AioContext;
diff --git a/include/system/accel-ops.h b/include/system/accel-ops.h
index 137fb96d444..4c99d25aeff 100644
--- a/include/system/accel-ops.h
+++ b/include/system/accel-ops.h
@@ -17,7 +17,6 @@
#define TYPE_ACCEL_OPS "accel" ACCEL_OPS_SUFFIX
#define ACCEL_OPS_NAME(name) (name "-" TYPE_ACCEL_OPS)
-typedef struct AccelOpsClass AccelOpsClass;
DECLARE_CLASS_CHECKERS(AccelOpsClass, ACCEL_OPS, TYPE_ACCEL_OPS)
/**
diff --git a/include/system/cpus.h b/include/system/cpus.h
index 1cffeaaf5c4..3226c765d01 100644
--- a/include/system/cpus.h
+++ b/include/system/cpus.h
@@ -1,8 +1,6 @@
#ifndef QEMU_CPUS_H
#define QEMU_CPUS_H
-#include "system/accel-ops.h"
-
/* register accel-specific operations */
void cpus_register_accel(const AccelOpsClass *i);
diff --git a/accel/accel-system.c b/accel/accel-system.c
index a7596aef59d..5df49fbe831 100644
--- a/accel/accel-system.c
+++ b/accel/accel-system.c
@@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
#include "hw/boards.h"
+#include "system/accel-ops.h"
#include "system/cpus.h"
#include "qemu/error-report.h"
#include "accel-system.h"
diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
index 945ba720513..12fc30c2761 100644
--- a/accel/hvf/hvf-accel-ops.c
+++ b/accel/hvf/hvf-accel-ops.c
@@ -54,6 +54,7 @@
#include "exec/exec-all.h"
#include "gdbstub/enums.h"
#include "hw/boards.h"
+#include "system/accel-ops.h"
#include "system/cpus.h"
#include "system/hvf.h"
#include "system/hvf_int.h"
diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c
index a81e8f3b03b..54ea60909e2 100644
--- a/accel/kvm/kvm-accel-ops.c
+++ b/accel/kvm/kvm-accel-ops.c
@@ -16,6 +16,7 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
+#include "system/accel-ops.h"
#include "system/kvm.h"
#include "system/kvm_int.h"
#include "system/runstate.h"
diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c
index ad7e3441a5a..7fae80f6a1b 100644
--- a/accel/qtest/qtest.c
+++ b/accel/qtest/qtest.c
@@ -18,6 +18,7 @@
#include "qemu/option.h"
#include "qemu/config-file.h"
#include "qemu/accel.h"
+#include "system/accel-ops.h"
#include "system/qtest.h"
#include "system/cpus.h"
#include "qemu/guest-random.h"
diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c
index 100746d555a..c5c513f1e4a 100644
--- a/accel/tcg/cpu-exec-common.c
+++ b/accel/tcg/cpu-exec-common.c
@@ -19,7 +19,6 @@
#include "qemu/osdep.h"
#include "exec/log.h"
-#include "system/cpus.h"
#include "system/tcg.h"
#include "qemu/plugin.h"
#include "internal-common.h"
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 3a3c45f52ed..ef3d967e3af 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -33,7 +33,6 @@
#include "qemu/rcu.h"
#include "exec/log.h"
#include "qemu/main-loop.h"
-#include "system/cpus.h"
#include "exec/cpu-all.h"
#include "system/cpu-timers.h"
#include "exec/replay-core.h"
diff --git a/accel/tcg/monitor.c b/accel/tcg/monitor.c
index ae1dbeb79f8..eeb38a4d9ce 100644
--- a/accel/tcg/monitor.c
+++ b/accel/tcg/monitor.c
@@ -13,7 +13,6 @@
#include "qapi/type-helpers.h"
#include "qapi/qapi-commands-machine.h"
#include "monitor/monitor.h"
-#include "system/cpus.h"
#include "system/cpu-timers.h"
#include "system/tcg.h"
#include "tcg/tcg.h"
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 6e3f1fa92b2..132c5d14613 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -26,6 +26,7 @@
*/
#include "qemu/osdep.h"
+#include "system/accel-ops.h"
#include "system/tcg.h"
#include "system/replay.h"
#include "system/cpu-timers.h"
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 786e2f6f1a7..0914d6e98b2 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -54,7 +54,6 @@
#include "qemu/cacheinfo.h"
#include "qemu/timer.h"
#include "exec/log.h"
-#include "system/cpus.h"
#include "system/cpu-timers.h"
#include "system/tcg.h"
#include "qapi/error.h"
diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c
index 852e9fbe5fe..7aa28b9ab93 100644
--- a/accel/xen/xen-all.c
+++ b/accel/xen/xen-all.c
@@ -18,6 +18,7 @@
#include "hw/xen/xen_igd.h"
#include "chardev/char.h"
#include "qemu/accel.h"
+#include "system/accel-ops.h"
#include "system/cpus.h"
#include "system/xen.h"
#include "system/runstate.h"
diff --git a/cpu-common.c b/cpu-common.c
index 4248b2d727e..f5dcc2d136b 100644
--- a/cpu-common.c
+++ b/cpu-common.c
@@ -21,7 +21,6 @@
#include "qemu/main-loop.h"
#include "exec/cpu-common.h"
#include "hw/core/cpu.h"
-#include "system/cpus.h"
#include "qemu/lockable.h"
#include "trace/trace-root.h"
diff --git a/cpu-target.c b/cpu-target.c
index f97f3a14751..20933bde7d4 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -35,6 +35,7 @@
#include "exec/address-spaces.h"
#include "exec/memory.h"
#endif
+#include "system/accel-ops.h"
#include "system/cpus.h"
#include "system/tcg.h"
#include "exec/tswap.h"
diff --git a/gdbstub/system.c b/gdbstub/system.c
index 7f047a285c8..416c1dbe1e9 100644
--- a/gdbstub/system.c
+++ b/gdbstub/system.c
@@ -19,6 +19,7 @@
#include "gdbstub/commands.h"
#include "exec/hwaddr.h"
#include "exec/tb-flush.h"
+#include "system/accel-ops.h"
#include "system/cpus.h"
#include "system/runstate.h"
#include "system/replay.h"
diff --git a/system/cpus.c b/system/cpus.c
index 37e5892c240..2cc5f887ab5 100644
--- a/system/cpus.c
+++ b/system/cpus.c
@@ -31,6 +31,7 @@
#include "qapi/qapi-events-run-state.h"
#include "qapi/qmp/qerror.h"
#include "exec/gdbstub.h"
+#include "system/accel-ops.h"
#include "system/hw_accel.h"
#include "exec/cpu-common.h"
#include "qemu/thread.h"
diff --git a/target/i386/nvmm/nvmm-accel-ops.c b/target/i386/nvmm/nvmm-accel-ops.c
index e7b56662fee..4e4e63de78e 100644
--- a/target/i386/nvmm/nvmm-accel-ops.c
+++ b/target/i386/nvmm/nvmm-accel-ops.c
@@ -10,6 +10,7 @@
#include "qemu/osdep.h"
#include "system/kvm_int.h"
#include "qemu/main-loop.h"
+#include "system/accel-ops.h"
#include "system/cpus.h"
#include "qemu/guest-random.h"
diff --git a/target/i386/whpx/whpx-accel-ops.c b/target/i386/whpx/whpx-accel-ops.c
index ab2e014c9ea..81fdd06e487 100644
--- a/target/i386/whpx/whpx-accel-ops.c
+++ b/target/i386/whpx/whpx-accel-ops.c
@@ -11,6 +11,7 @@
#include "qemu/osdep.h"
#include "system/kvm_int.h"
#include "qemu/main-loop.h"
+#include "system/accel-ops.h"
#include "system/cpus.h"
#include "qemu/guest-random.h"
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 14/54] accel/accel-cpu-target.h: Include missing 'cpu.h' header
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2025-03-06 15:46 ` [PULL 13/54] accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h' Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 15/54] accel/tcg: Include missing bswap headers in user-exec.c Philippe Mathieu-Daudé
` (40 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
CPU_RESOLVING_TYPE is declared per target in "cpu.h". Include
it (along with "qom/object.h") to avoid when moving code around:
include/accel/accel-cpu-target.h:26:50: error: expected ')'
26 | DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
| ^
include/accel/accel-cpu-target.h:23:33: note: expanded from macro 'TYPE_ACCEL_CPU'
23 | #define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
| ^
include/accel/accel-cpu-target.h:26:1: note: to match this '('
26 | DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
| ^
include/qom/object.h:196:14: note: expanded from macro 'DECLARE_CLASS_CHECKERS'
196 | { return OBJECT_GET_CLASS(ClassType, obj, TYPENAME); } \
| ^
include/qom/object.h:558:5: note: expanded from macro 'OBJECT_GET_CLASS'
558 | OBJECT_CLASS_CHECK(class, object_get_class(OBJECT(obj)), name)
| ^
include/qom/object.h:544:74: note: expanded from macro 'OBJECT_CLASS_CHECK'
544 | ((class_type *)object_class_dynamic_cast_assert(OBJECT_CLASS(class), (name), \
| ^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-13-philmd@linaro.org>
---
include/accel/accel-cpu-target.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/accel/accel-cpu-target.h b/include/accel/accel-cpu-target.h
index 0a8e518600d..37dde7fae3e 100644
--- a/include/accel/accel-cpu-target.h
+++ b/include/accel/accel-cpu-target.h
@@ -20,6 +20,9 @@
* subclasses in target/, or the accel implementation itself in accel/
*/
+#include "qom/object.h"
+#include "cpu.h"
+
#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
typedef struct AccelCPUClass AccelCPUClass;
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 15/54] accel/tcg: Include missing bswap headers in user-exec.c
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2025-03-06 15:46 ` [PULL 14/54] accel/accel-cpu-target.h: Include missing 'cpu.h' header Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 16/54] accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() function Philippe Mathieu-Daudé
` (39 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
Commit 35c653c4029 ("tcg: Add 128-bit guest memory
primitives") introduced the use of bswap128() which is
declared in "qemu/int128.h", commit de95016dfbf ("accel/tcg:
Implement helper_{ld,st}*_mmu for user-only") introduced the
other bswap*() uses, which are declared in "qemu/bswap.h".
Include the missing headers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250217130610.18313-3-philmd@linaro.org>
---
accel/tcg/user-exec.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index c4454100ad7..9d53c9440ea 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -30,6 +30,8 @@
#include "exec/page-protection.h"
#include "exec/helper-proto.h"
#include "qemu/atomic128.h"
+#include "qemu/bswap.h"
+#include "qemu/int128.h"
#include "trace.h"
#include "tcg/tcg-ldst.h"
#include "internal-common.h"
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 16/54] accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() function
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2025-03-06 15:46 ` [PULL 15/54] accel/tcg: Include missing bswap headers in user-exec.c Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 17/54] accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug() Philippe Mathieu-Daudé
` (38 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
Simplify user implementation of cpu_memory_rw_debug() by
taking the mmap lock globally. See commit 87ab2704296
("linux-user: Allow gdbstub to ignore page protection")
for why this lock is necessary.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250217130610.18313-4-philmd@linaro.org>
---
cpu-target.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index 20933bde7d4..b5230ce1837 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -380,6 +380,8 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
int ret = -1;
int fd = -1;
+ mmap_lock();
+
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
l = (page + TARGET_PAGE_SIZE) - addr;
@@ -414,11 +416,9 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
* be under mmap_lock() in order to prevent the creation of
* another TranslationBlock in between.
*/
- mmap_lock();
tb_invalidate_phys_range(addr, addr + l - 1);
written = pwrite(fd, buf, l,
(off_t)(uintptr_t)g2h_untagged(addr));
- mmap_unlock();
if (written != l) {
goto out_close;
}
@@ -454,6 +454,8 @@ out_close:
close(fd);
}
out:
+ mmap_unlock();
+
return ret;
}
#endif
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 17/54] accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2025-03-06 15:46 ` [PULL 16/54] accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() function Philippe Mathieu-Daudé
@ 2025-03-06 15:46 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 18/54] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c Philippe Mathieu-Daudé
` (37 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:46 UTC (permalink / raw)
To: qemu-devel
We checked the page flags with page_get_flags(), so
locking the page is superfluous. Remove the lock_user()
calls and directly use g2h() in place.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250217130610.18313-5-philmd@linaro.org>
---
cpu-target.c | 17 ++---------------
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index b5230ce1837..3892ce12229 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -374,7 +374,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
{
int flags;
vaddr l, page;
- void * p;
uint8_t *buf = ptr;
ssize_t written;
int ret = -1;
@@ -393,13 +392,7 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
}
if (is_write) {
if (flags & PAGE_WRITE) {
- /* XXX: this code should not depend on lock_user */
- p = lock_user(VERIFY_WRITE, addr, l, 0);
- if (!p) {
- goto out_close;
- }
- memcpy(p, buf, l);
- unlock_user(p, addr, l);
+ memcpy(g2h(cpu, addr), buf, l);
} else {
/* Bypass the host page protection using ptrace. */
if (fd == -1) {
@@ -424,13 +417,7 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
}
}
} else if (flags & PAGE_READ) {
- /* XXX: this code should not depend on lock_user */
- p = lock_user(VERIFY_READ, addr, l, 1);
- if (!p) {
- goto out_close;
- }
- memcpy(buf, p, l);
- unlock_user(p, addr, 0);
+ memcpy(buf, g2h(cpu, addr), l);
} else {
/* Bypass the host page protection using ptrace. */
if (fd == -1) {
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 18/54] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2025-03-06 15:46 ` [PULL 17/54] accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug() Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 19/54] accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h Philippe Mathieu-Daudé
` (36 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
cpu_memory_rw_debug() system implementation is defined in
system/physmem.c. Move the user one to accel/tcg/user-exec.c
to simplify cpu-target.c maintenance.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250217130610.18313-6-philmd@linaro.org>
---
accel/tcg/user-exec.c | 80 ++++++++++++++++++++++++++++++++++++++
cpu-target.c | 90 +------------------------------------------
2 files changed, 82 insertions(+), 88 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 9d53c9440ea..2322181b151 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "accel/tcg/cpu-ops.h"
#include "disas/disas.h"
+#include "exec/vaddr.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"
#include "qemu/bitops.h"
@@ -971,6 +972,85 @@ static void *cpu_mmu_lookup(CPUState *cpu, vaddr addr,
return ret;
}
+/* physical memory access (slow version, mainly for debug) */
+int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
+ void *ptr, size_t len, bool is_write)
+{
+ int flags;
+ vaddr l, page;
+ uint8_t *buf = ptr;
+ ssize_t written;
+ int ret = -1;
+ int fd = -1;
+
+ mmap_lock();
+
+ while (len > 0) {
+ page = addr & TARGET_PAGE_MASK;
+ l = (page + TARGET_PAGE_SIZE) - addr;
+ if (l > len) {
+ l = len;
+ }
+ flags = page_get_flags(page);
+ if (!(flags & PAGE_VALID)) {
+ goto out_close;
+ }
+ if (is_write) {
+ if (flags & PAGE_WRITE) {
+ memcpy(g2h(cpu, addr), buf, l);
+ } else {
+ /* Bypass the host page protection using ptrace. */
+ if (fd == -1) {
+ fd = open("/proc/self/mem", O_WRONLY);
+ if (fd == -1) {
+ goto out;
+ }
+ }
+ /*
+ * If there is a TranslationBlock and we weren't bypassing the
+ * host page protection, the memcpy() above would SEGV,
+ * ultimately leading to page_unprotect(). So invalidate the
+ * translations manually. Both invalidation and pwrite() must
+ * be under mmap_lock() in order to prevent the creation of
+ * another TranslationBlock in between.
+ */
+ tb_invalidate_phys_range(addr, addr + l - 1);
+ written = pwrite(fd, buf, l,
+ (off_t)(uintptr_t)g2h_untagged(addr));
+ if (written != l) {
+ goto out_close;
+ }
+ }
+ } else if (flags & PAGE_READ) {
+ memcpy(buf, g2h(cpu, addr), l);
+ } else {
+ /* Bypass the host page protection using ptrace. */
+ if (fd == -1) {
+ fd = open("/proc/self/mem", O_RDONLY);
+ if (fd == -1) {
+ goto out;
+ }
+ }
+ if (pread(fd, buf, l,
+ (off_t)(uintptr_t)g2h_untagged(addr)) != l) {
+ goto out_close;
+ }
+ }
+ len -= l;
+ buf += l;
+ addr += l;
+ }
+ ret = 0;
+out_close:
+ if (fd != -1) {
+ close(fd);
+ }
+out:
+ mmap_unlock();
+
+ return ret;
+}
+
#include "ldst_atomicity.c.inc"
static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,
diff --git a/cpu-target.c b/cpu-target.c
index 3892ce12229..83688f1d508 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -19,18 +19,12 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-
-#include "exec/target_page.h"
-#include "exec/page-protection.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "qemu/qemu-print.h"
#include "migration/vmstate.h"
-#ifdef CONFIG_USER_ONLY
-#include "qemu.h"
-#include "user/page-protection.h"
-#else
+#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#include "exec/memory.h"
@@ -43,11 +37,11 @@
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
#include "exec/tb-flush.h"
-#include "exec/translation-block.h"
#include "exec/log.h"
#include "accel/accel-cpu-target.h"
#include "trace/trace-root.h"
#include "qemu/accel.h"
+#include "hw/core/cpu.h"
#ifndef CONFIG_USER_ONLY
static int cpu_common_post_load(void *opaque, int version_id)
@@ -367,86 +361,6 @@ void cpu_abort(CPUState *cpu, const char *fmt, ...)
abort();
}
-/* physical memory access (slow version, mainly for debug) */
-#if defined(CONFIG_USER_ONLY)
-int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
- void *ptr, size_t len, bool is_write)
-{
- int flags;
- vaddr l, page;
- uint8_t *buf = ptr;
- ssize_t written;
- int ret = -1;
- int fd = -1;
-
- mmap_lock();
-
- while (len > 0) {
- page = addr & TARGET_PAGE_MASK;
- l = (page + TARGET_PAGE_SIZE) - addr;
- if (l > len)
- l = len;
- flags = page_get_flags(page);
- if (!(flags & PAGE_VALID)) {
- goto out_close;
- }
- if (is_write) {
- if (flags & PAGE_WRITE) {
- memcpy(g2h(cpu, addr), buf, l);
- } else {
- /* Bypass the host page protection using ptrace. */
- if (fd == -1) {
- fd = open("/proc/self/mem", O_WRONLY);
- if (fd == -1) {
- goto out;
- }
- }
- /*
- * If there is a TranslationBlock and we weren't bypassing the
- * host page protection, the memcpy() above would SEGV,
- * ultimately leading to page_unprotect(). So invalidate the
- * translations manually. Both invalidation and pwrite() must
- * be under mmap_lock() in order to prevent the creation of
- * another TranslationBlock in between.
- */
- tb_invalidate_phys_range(addr, addr + l - 1);
- written = pwrite(fd, buf, l,
- (off_t)(uintptr_t)g2h_untagged(addr));
- if (written != l) {
- goto out_close;
- }
- }
- } else if (flags & PAGE_READ) {
- memcpy(buf, g2h(cpu, addr), l);
- } else {
- /* Bypass the host page protection using ptrace. */
- if (fd == -1) {
- fd = open("/proc/self/mem", O_RDONLY);
- if (fd == -1) {
- goto out;
- }
- }
- if (pread(fd, buf, l,
- (off_t)(uintptr_t)g2h_untagged(addr)) != l) {
- goto out_close;
- }
- }
- len -= l;
- buf += l;
- addr += l;
- }
- ret = 0;
-out_close:
- if (fd != -1) {
- close(fd);
- }
-out:
- mmap_unlock();
-
- return ret;
-}
-#endif
-
bool target_words_bigendian(void)
{
return TARGET_BIG_ENDIAN;
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 19/54] accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2025-03-06 15:47 ` [PULL 18/54] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 20/54] cpus: Fix style in cpu-target.c Philippe Mathieu-Daudé
` (35 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Missed in commit b86f59c7155 ("accel: replace struct CpusAccel
with AccelOpsClass") which removed the single CpusAccel use.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-7-philmd@linaro.org>
---
accel/kvm/kvm-cpus.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h
index b5435286e42..688511151c8 100644
--- a/accel/kvm/kvm-cpus.h
+++ b/accel/kvm/kvm-cpus.h
@@ -10,8 +10,6 @@
#ifndef KVM_CPUS_H
#define KVM_CPUS_H
-#include "system/cpus.h"
-
int kvm_init_vcpu(CPUState *cpu, Error **errp);
int kvm_cpu_exec(CPUState *cpu);
void kvm_destroy_vcpu(CPUState *cpu);
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 20/54] cpus: Fix style in cpu-target.c
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2025-03-06 15:47 ` [PULL 19/54] accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 21/54] cpus: Restrict cpu_common_post_load() code to TCG Philippe Mathieu-Daudé
` (34 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Fix style on code we are going to modify.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-16-philmd@linaro.org>
---
cpu-target.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index 83688f1d508..b925b9391e8 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -48,12 +48,15 @@ static int cpu_common_post_load(void *opaque, int version_id)
{
CPUState *cpu = opaque;
- /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
- version_id is increased. */
+ /*
+ * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
+ * version_id is increased.
+ */
cpu->interrupt_request &= ~0x01;
tlb_flush(cpu);
- /* loadvm has just updated the content of RAM, bypassing the
+ /*
+ * loadvm has just updated the content of RAM, bypassing the
* usual mechanisms that ensure we flush TBs for writes to
* memory we've translated code from. So we must flush all TBs,
* which will now be stale.
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 21/54] cpus: Restrict cpu_common_post_load() code to TCG
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2025-03-06 15:47 ` [PULL 20/54] cpus: Fix style in cpu-target.c Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 22/54] cpus: Have cpu_class_init_props() per user / system emulation Philippe Mathieu-Daudé
` (33 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
CPU_INTERRUPT_EXIT was removed in commit 3098dba01c7
("Use a dedicated function to request exit from execution
loop"), tlb_flush() and tb_flush() are related to TCG
accelerator.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-17-philmd@linaro.org>
---
cpu-target.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index b925b9391e8..48446c90212 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -46,22 +46,25 @@
#ifndef CONFIG_USER_ONLY
static int cpu_common_post_load(void *opaque, int version_id)
{
- CPUState *cpu = opaque;
+ if (tcg_enabled()) {
+ CPUState *cpu = opaque;
- /*
- * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
- * version_id is increased.
- */
- cpu->interrupt_request &= ~0x01;
- tlb_flush(cpu);
+ /*
+ * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
+ * version_id is increased.
+ */
+ cpu->interrupt_request &= ~0x01;
- /*
- * loadvm has just updated the content of RAM, bypassing the
- * usual mechanisms that ensure we flush TBs for writes to
- * memory we've translated code from. So we must flush all TBs,
- * which will now be stale.
- */
- tb_flush(cpu);
+ tlb_flush(cpu);
+
+ /*
+ * loadvm has just updated the content of RAM, bypassing the
+ * usual mechanisms that ensure we flush TBs for writes to
+ * memory we've translated code from. So we must flush all TBs,
+ * which will now be stale.
+ */
+ tb_flush(cpu);
+ }
return 0;
}
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 22/54] cpus: Have cpu_class_init_props() per user / system emulation
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (20 preceding siblings ...)
2025-03-06 15:47 ` [PULL 21/54] cpus: Restrict cpu_common_post_load() code to TCG Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 23/54] cpus: Have cpu_exec_initfn() " Philippe Mathieu-Daudé
` (32 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Rather than maintaining a mix of system / user code for CPU
class properties, move system properties to cpu-system.c
and user ones to the new cpu-user.c unit.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-18-philmd@linaro.org>
---
MAINTAINERS | 1 +
cpu-target.c | 58 --------------------------------------------
hw/core/cpu-system.c | 40 ++++++++++++++++++++++++++++++
hw/core/cpu-user.c | 27 +++++++++++++++++++++
hw/core/meson.build | 5 +++-
5 files changed, 72 insertions(+), 59 deletions(-)
create mode 100644 hw/core/cpu-user.c
diff --git a/MAINTAINERS b/MAINTAINERS
index a0e462d03ca..1d1fadc3bc9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3791,6 +3791,7 @@ Overall usermode emulation
M: Riku Voipio <riku.voipio@iki.fi>
S: Maintained
F: accel/tcg/user-exec*.c
+F: hw/core/cpu-user.c
F: include/user/
F: common-user/
diff --git a/cpu-target.c b/cpu-target.c
index 48446c90212..f4c834fd26a 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -19,15 +19,12 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/qdev-core.h"
-#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "qemu/qemu-print.h"
#include "migration/vmstate.h"
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
-#include "exec/memory.h"
#endif
#include "system/accel-ops.h"
#include "system/cpus.h"
@@ -178,61 +175,6 @@ void cpu_exec_unrealizefn(CPUState *cpu)
accel_cpu_common_unrealize(cpu);
}
-/*
- * This can't go in hw/core/cpu.c because that file is compiled only
- * once for both user-mode and system builds.
- */
-static const Property cpu_common_props[] = {
-#ifdef CONFIG_USER_ONLY
- /*
- * Create a property for the user-only object, so users can
- * adjust prctl(PR_SET_UNALIGN) from the command-line.
- * Has no effect if the target does not support the feature.
- */
- DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
- prctl_unalign_sigbus, false),
-#else
- /*
- * Create a memory property for system CPU object, so users can
- * wire up its memory. The default if no link is set up is to use
- * the system address space.
- */
- DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
- MemoryRegion *),
-#endif
-};
-
-#ifndef CONFIG_USER_ONLY
-static bool cpu_get_start_powered_off(Object *obj, Error **errp)
-{
- CPUState *cpu = CPU(obj);
- return cpu->start_powered_off;
-}
-
-static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
-{
- CPUState *cpu = CPU(obj);
- cpu->start_powered_off = value;
-}
-#endif
-
-void cpu_class_init_props(DeviceClass *dc)
-{
-#ifndef CONFIG_USER_ONLY
- ObjectClass *oc = OBJECT_CLASS(dc);
-
- /*
- * We can't use DEFINE_PROP_BOOL in the Property array for this
- * property, because we want this to be settable after realize.
- */
- object_class_property_add_bool(oc, "start-powered-off",
- cpu_get_start_powered_off,
- cpu_set_start_powered_off);
-#endif
-
- device_class_set_props(dc, cpu_common_props);
-}
-
void cpu_exec_initfn(CPUState *cpu)
{
#ifndef CONFIG_USER_ONLY
diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c
index 6e307c89597..1310b4203fd 100644
--- a/hw/core/cpu-system.c
+++ b/hw/core/cpu-system.c
@@ -20,7 +20,10 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
+#include "exec/memory.h"
#include "exec/tswap.h"
+#include "hw/qdev-core.h"
+#include "hw/qdev-properties.h"
#include "hw/core/sysemu-cpu-ops.h"
bool cpu_paging_enabled(const CPUState *cpu)
@@ -147,3 +150,40 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
}
return res;
}
+
+static const Property cpu_system_props[] = {
+ /*
+ * Create a memory property for system CPU object, so users can
+ * wire up its memory. The default if no link is set up is to use
+ * the system address space.
+ */
+ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+};
+
+static bool cpu_get_start_powered_off(Object *obj, Error **errp)
+{
+ CPUState *cpu = CPU(obj);
+ return cpu->start_powered_off;
+}
+
+static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
+{
+ CPUState *cpu = CPU(obj);
+ cpu->start_powered_off = value;
+}
+
+void cpu_class_init_props(DeviceClass *dc)
+{
+ ObjectClass *oc = OBJECT_CLASS(dc);
+
+ /*
+ * We can't use DEFINE_PROP_BOOL in the Property array for this
+ * property, because we want this to be settable after realize.
+ */
+ object_class_property_add_bool(oc, "start-powered-off",
+ cpu_get_start_powered_off,
+ cpu_set_start_powered_off);
+
+ device_class_set_props(dc, cpu_system_props);
+}
diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c
new file mode 100644
index 00000000000..e5ccf6bf13a
--- /dev/null
+++ b/hw/core/cpu-user.c
@@ -0,0 +1,27 @@
+/*
+ * QEMU CPU model (user specific)
+ *
+ * Copyright (c) Linaro, Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/qdev-core.h"
+#include "hw/qdev-properties.h"
+#include "hw/core/cpu.h"
+
+static const Property cpu_user_props[] = {
+ /*
+ * Create a property for the user-only object, so users can
+ * adjust prctl(PR_SET_UNALIGN) from the command-line.
+ * Has no effect if the target does not support the feature.
+ */
+ DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
+ prctl_unalign_sigbus, false),
+};
+
+void cpu_class_init_props(DeviceClass *dc)
+{
+ device_class_set_props(dc, cpu_user_props);
+}
diff --git a/hw/core/meson.build b/hw/core/meson.build
index 65a1698ed1f..b5a545a0edd 100644
--- a/hw/core/meson.build
+++ b/hw/core/meson.build
@@ -46,4 +46,7 @@ system_ss.add(files(
'vm-change-state-handler.c',
'clock-vmstate.c',
))
-user_ss.add(files('qdev-user.c'))
+user_ss.add(files(
+ 'cpu-user.c',
+ 'qdev-user.c',
+))
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 23/54] cpus: Have cpu_exec_initfn() per user / system emulation
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (21 preceding siblings ...)
2025-03-06 15:47 ` [PULL 22/54] cpus: Have cpu_class_init_props() per user / system emulation Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 24/54] cpus: Restrict cpu_get_memory_mapping() to " Philippe Mathieu-Daudé
` (31 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Slighly simplify cpu-target.c again by extracting cpu_exec_initfn()
to cpu-{system,user}.c, adding an empty stub for user emulation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-19-philmd@linaro.org>
---
cpu-target.c | 9 ---------
hw/core/cpu-system.c | 7 +++++++
hw/core/cpu-user.c | 5 +++++
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index f4c834fd26a..5aa6c4b0c63 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -24,7 +24,6 @@
#include "migration/vmstate.h"
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
-#include "exec/address-spaces.h"
#endif
#include "system/accel-ops.h"
#include "system/cpus.h"
@@ -175,14 +174,6 @@ void cpu_exec_unrealizefn(CPUState *cpu)
accel_cpu_common_unrealize(cpu);
}
-void cpu_exec_initfn(CPUState *cpu)
-{
-#ifndef CONFIG_USER_ONLY
- cpu->memory = get_system_memory();
- object_ref(OBJECT(cpu->memory));
-#endif
-}
-
char *cpu_model_from_type(const char *typename)
{
const char *suffix = "-" CPU_RESOLVING_TYPE;
diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c
index 1310b4203fd..e511507e13b 100644
--- a/hw/core/cpu-system.c
+++ b/hw/core/cpu-system.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
+#include "exec/address-spaces.h"
#include "exec/memory.h"
#include "exec/tswap.h"
#include "hw/qdev-core.h"
@@ -187,3 +188,9 @@ void cpu_class_init_props(DeviceClass *dc)
device_class_set_props(dc, cpu_system_props);
}
+
+void cpu_exec_initfn(CPUState *cpu)
+{
+ cpu->memory = get_system_memory();
+ object_ref(OBJECT(cpu->memory));
+}
diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c
index e5ccf6bf13a..cdd8de2fefa 100644
--- a/hw/core/cpu-user.c
+++ b/hw/core/cpu-user.c
@@ -25,3 +25,8 @@ void cpu_class_init_props(DeviceClass *dc)
{
device_class_set_props(dc, cpu_user_props);
}
+
+void cpu_exec_initfn(CPUState *cpu)
+{
+ /* nothing to do */
+}
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 24/54] cpus: Restrict cpu_get_memory_mapping() to system emulation
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (22 preceding siblings ...)
2025-03-06 15:47 ` [PULL 23/54] cpus: Have cpu_exec_initfn() " Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 25/54] hw/core/generic-loader: Do not open-code cpu_set_pc() Philippe Mathieu-Daudé
` (30 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250121142341.17001-5-philmd@linaro.org>
---
include/hw/core/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 7b6b22c431b..9dd6ac7c763 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -616,6 +616,8 @@ extern bool mttcg_enabled;
*/
bool cpu_paging_enabled(const CPUState *cpu);
+#if !defined(CONFIG_USER_ONLY)
+
/**
* cpu_get_memory_mapping:
* @cpu: The CPU whose memory mappings are to be obtained.
@@ -627,8 +629,6 @@ bool cpu_paging_enabled(const CPUState *cpu);
bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
Error **errp);
-#if !defined(CONFIG_USER_ONLY)
-
/**
* cpu_write_elf64_note:
* @f: pointer to a function that writes memory to a file
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 25/54] hw/core/generic-loader: Do not open-code cpu_set_pc()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (23 preceding siblings ...)
2025-03-06 15:47 ` [PULL 24/54] cpus: Restrict cpu_get_memory_mapping() to " Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 26/54] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
` (29 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Directly call cpu_set_pc() instead of open-coding it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250122093028.52416-2-philmd@linaro.org>
---
hw/core/generic-loader.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
index d9f5c2e8325..d3a426a1a26 100644
--- a/hw/core/generic-loader.c
+++ b/hw/core/generic-loader.c
@@ -47,11 +47,8 @@ static void generic_loader_reset(void *opaque)
GenericLoaderState *s = GENERIC_LOADER(opaque);
if (s->set_pc) {
- CPUClass *cc = CPU_GET_CLASS(s->cpu);
cpu_reset(s->cpu);
- if (cc) {
- cc->set_pc(s->cpu, s->addr);
- }
+ cpu_set_pc(s->cpu, s->addr);
}
if (s->data_len) {
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 26/54] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (24 preceding siblings ...)
2025-03-06 15:47 ` [PULL 25/54] hw/core/generic-loader: Do not open-code cpu_set_pc() Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 27/54] target/microblaze: Set MO_TE once in do_load() / do_store() Philippe Mathieu-Daudé
` (28 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/microblaze); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20241105130431.22564-14-philmd@linaro.org>
---
target/microblaze/translate.c | 36 +++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 24005f05b21..86efabb83b5 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -780,13 +780,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
static bool trans_lhu(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_lhur(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
}
static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
@@ -798,26 +798,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_lw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_lwr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
}
static bool trans_lwea(DisasContext *dc, arg_typea *arg)
@@ -829,14 +829,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_lwx(DisasContext *dc, arg_typea *arg)
@@ -846,7 +846,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
/* lwx does not throw unaligned access errors, so force alignment */
tcg_gen_andi_tl(addr, addr, ~3);
- tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
+ tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL);
tcg_gen_mov_tl(cpu_res_addr, addr);
if (arg->rd) {
@@ -930,13 +930,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
static bool trans_sh(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_shr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
}
static bool trans_shea(DisasContext *dc, arg_typea *arg)
@@ -948,26 +948,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_shi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_sw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_swr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
}
static bool trans_swea(DisasContext *dc, arg_typea *arg)
@@ -979,14 +979,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_swi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_swx(DisasContext *dc, arg_typea *arg)
@@ -1015,7 +1015,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val,
reg_for_write(dc, arg->rd),
- dc->mem_index, MO_TEUL);
+ dc->mem_index, MO_TE | MO_UL);
tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 27/54] target/microblaze: Set MO_TE once in do_load() / do_store()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (25 preceding siblings ...)
2025-03-06 15:47 ` [PULL 26/54] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 28/54] target/microblaze: Introduce mo_endian() helper Philippe Mathieu-Daudé
` (27 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
All callers of do_load() / do_store() set MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241105130431.22564-15-philmd@linaro.org>
---
target/microblaze/translate.c | 36 +++++++++++++++++++----------------
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 86efabb83b5..0d51b2c468c 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -713,6 +713,8 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
{
MemOp size = mop & MO_SIZE;
+ mop |= MO_TE;
+
/*
* When doing reverse accesses we need to do two things.
*
@@ -780,13 +782,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
static bool trans_lhu(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_lhur(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
+ return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
}
static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
@@ -798,26 +800,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
+ return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_lw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_lwr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
+ return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
}
static bool trans_lwea(DisasContext *dc, arg_typea *arg)
@@ -829,14 +831,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
+ return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_lwx(DisasContext *dc, arg_typea *arg)
@@ -863,6 +865,8 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
{
MemOp size = mop & MO_SIZE;
+ mop |= MO_TE;
+
/*
* When doing reverse accesses we need to do two things.
*
@@ -930,13 +934,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
static bool trans_sh(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_shr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
+ return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
}
static bool trans_shea(DisasContext *dc, arg_typea *arg)
@@ -948,26 +952,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
+ return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_shi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_sw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_swr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
+ return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
}
static bool trans_swea(DisasContext *dc, arg_typea *arg)
@@ -979,14 +983,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
+ return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_swi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_swx(DisasContext *dc, arg_typea *arg)
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 28/54] target/microblaze: Introduce mo_endian() helper
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (26 preceding siblings ...)
2025-03-06 15:47 ` [PULL 27/54] target/microblaze: Set MO_TE once in do_load() / do_store() Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 29/54] target/microblaze: Consider endianness while translating code Philippe Mathieu-Daudé
` (26 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
mo_endian() returns the target endianness, currently static.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241105130431.22564-16-philmd@linaro.org>
---
target/microblaze/translate.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 0d51b2c468c..b5389d65b2e 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -708,12 +708,17 @@ static void record_unaligned_ess(DisasContext *dc, int rd,
}
#endif
+static inline MemOp mo_endian(DisasContext *dc)
+{
+ return MO_TE;
+}
+
static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
int mem_index, bool rev)
{
MemOp size = mop & MO_SIZE;
- mop |= MO_TE;
+ mop |= mo_endian(dc);
/*
* When doing reverse accesses we need to do two things.
@@ -848,7 +853,8 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
/* lwx does not throw unaligned access errors, so force alignment */
tcg_gen_andi_tl(addr, addr, ~3);
- tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL);
+ tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index,
+ mo_endian(dc) | MO_UL);
tcg_gen_mov_tl(cpu_res_addr, addr);
if (arg->rd) {
@@ -865,7 +871,7 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
{
MemOp size = mop & MO_SIZE;
- mop |= MO_TE;
+ mop |= mo_endian(dc);
/*
* When doing reverse accesses we need to do two things.
@@ -1019,7 +1025,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val,
reg_for_write(dc, arg->rd),
- dc->mem_index, MO_TE | MO_UL);
+ dc->mem_index, mo_endian(dc) | MO_UL);
tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 29/54] target/microblaze: Consider endianness while translating code
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (27 preceding siblings ...)
2025-03-06 15:47 ` [PULL 28/54] target/microblaze: Introduce mo_endian() helper Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 30/54] target/i386/hvf: Variable type fixup in decoder Philippe Mathieu-Daudé
` (25 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Consider the CPU ENDI bit, swap instructions when the CPU
endianness doesn't match the binary one.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241105130431.22564-17-philmd@linaro.org>
---
target/microblaze/cpu.h | 7 +++++++
target/microblaze/translate.c | 5 +++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index f6879eee352..e44ddd53078 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -414,6 +414,13 @@ void mb_translate_code(CPUState *cs, TranslationBlock *tb,
/* Ensure there is no overlap between the two masks. */
QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
+static inline bool mb_cpu_is_big_endian(CPUState *cs)
+{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+
+ return !cpu->cfg.endi;
+}
+
static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index b5389d65b2e..b54e5ac4b2f 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -710,7 +710,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd,
static inline MemOp mo_endian(DisasContext *dc)
{
- return MO_TE;
+ return dc->cfg->endi ? MO_LE : MO_BE;
}
static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
@@ -1647,7 +1647,8 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
dc->tb_flags_to_set = 0;
- ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next);
+ ir = translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next,
+ mb_cpu_is_big_endian(cs) != TARGET_BIG_ENDIAN);
if (!decode(dc, ir)) {
trap_illegal(dc, true);
}
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 30/54] target/i386/hvf: Variable type fixup in decoder
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (28 preceding siblings ...)
2025-03-06 15:47 ` [PULL 29/54] target/microblaze: Consider endianness while translating code Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 31/54] target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize() Philippe Mathieu-Daudé
` (24 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
From: Phil Dennis-Jordan <phil@philjordan.eu>
decode_bytes reads 1, 2, 4, or 8 bytes at a time. The destination
variable should therefore be a uint64_t, not a target_ulong.
Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu>
Fixes: ff2de1668c9 ("i386: hvf: remove addr_t")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241209203629.74436-9-phil@philjordan.eu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/i386/hvf/x86_decode.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c
index d6d5894e54b..5fea2dd3cc0 100644
--- a/target/i386/hvf/x86_decode.c
+++ b/target/i386/hvf/x86_decode.c
@@ -61,8 +61,8 @@ uint64_t sign(uint64_t val, int size)
static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode,
int size)
{
- target_ulong val = 0;
-
+ uint64_t val = 0;
+
switch (size) {
case 1:
case 2:
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 31/54] target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (29 preceding siblings ...)
2025-03-06 15:47 ` [PULL 30/54] target/i386/hvf: Variable type fixup in decoder Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 32/54] target/hexagon: Ensure not being build on system emulation Philippe Mathieu-Daudé
` (23 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
OpenRISC timer is architecturally tied to the CPU.
It doesn't belong to the machine init() code to
instanciate it: move its creation when a vCPU is
realized (after being created).
Reported-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250114231304.77150-1-philmd@linaro.org>
---
hw/openrisc/openrisc_sim.c | 2 --
hw/openrisc/virt.c | 2 --
target/openrisc/cpu.c | 4 ++++
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index d9e0744922a..83d7c2a8afc 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -306,8 +306,6 @@ static void openrisc_sim_init(MachineState *machine)
exit(1);
}
- cpu_openrisc_clock_init(cpus[n]);
-
qemu_register_reset(main_cpu_reset, cpus[n]);
}
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
index 9afe407b00a..3055306783e 100644
--- a/hw/openrisc/virt.c
+++ b/hw/openrisc/virt.c
@@ -487,8 +487,6 @@ static void openrisc_virt_init(MachineState *machine)
exit(1);
}
- cpu_openrisc_clock_init(cpus[n]);
-
qemu_register_reset(main_cpu_reset, cpus[n]);
}
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 0669ba2fd10..785b065b513 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -165,6 +165,10 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
qemu_init_vcpu(cs);
cpu_reset(cs);
+#ifndef CONFIG_USER_ONLY
+ cpu_openrisc_clock_init(OPENRISC_CPU(dev));
+#endif
+
occ->parent_realize(dev, errp);
}
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 32/54] target/hexagon: Ensure not being build on system emulation
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (30 preceding siblings ...)
2025-03-06 15:47 ` [PULL 31/54] target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize() Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 33/54] target/rx: Ensure not being build on user emulation Philippe Mathieu-Daudé
` (22 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Currently only user emulation is supported.
Assert no target code is built for system emulation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Message-Id: <20250121142341.17001-2-philmd@linaro.org>
---
target/hexagon/cpu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 79e60d4bfa1..f78c8f9c2a0 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -26,6 +26,10 @@
#include "mmvec/mmvec.h"
#include "hw/registerfields.h"
+#ifndef CONFIG_USER_ONLY
+#error "Hexagon does not support system emulation"
+#endif
+
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 33/54] target/rx: Ensure not being build on user emulation
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (31 preceding siblings ...)
2025-03-06 15:47 ` [PULL 32/54] target/hexagon: Ensure not being build on system emulation Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 34/54] target/tricore: " Philippe Mathieu-Daudé
` (21 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Currently only system emulation is supported.
Assert no target code is built for user emulation.
Remove #ifdef'ry since more work is required before
being able to emulate a user process.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250121142341.17001-3-philmd@linaro.org>
---
target/rx/cpu.h | 6 ++++--
target/rx/cpu.c | 6 ------
target/rx/helper.c | 4 ----
3 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 5ba1874bd76..349d61c4e40 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -26,6 +26,10 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
+#ifdef CONFIG_USER_ONLY
+#error "RX does not support user mode emulation"
+#endif
+
/* PSW define */
REG32(PSW, 0)
FIELD(PSW, C, 0, 1)
@@ -129,11 +133,9 @@ struct RXCPUClass {
#define CPU_RESOLVING_TYPE TYPE_RX_CPU
const char *rx_crname(uint8_t cr);
-#ifndef CONFIG_USER_ONLY
void rx_cpu_do_interrupt(CPUState *cpu);
bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-#endif /* !CONFIG_USER_ONLY */
void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 7d5fcbf76ac..17ede51cd11 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -192,13 +192,11 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
-#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps rx_sysemu_ops = {
.get_phys_page_debug = rx_cpu_get_phys_page_debug,
};
-#endif
#include "accel/tcg/cpu-ops.h"
@@ -209,11 +207,9 @@ static const TCGCPUOps rx_tcg_ops = {
.restore_state_to_opc = rx_restore_state_to_opc,
.tlb_fill = rx_cpu_tlb_fill,
-#ifndef CONFIG_USER_ONLY
.cpu_exec_interrupt = rx_cpu_exec_interrupt,
.cpu_exec_halt = rx_cpu_has_work,
.do_interrupt = rx_cpu_do_interrupt,
-#endif /* !CONFIG_USER_ONLY */
};
static void rx_cpu_class_init(ObjectClass *klass, void *data)
@@ -235,9 +231,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->set_pc = rx_cpu_set_pc;
cc->get_pc = rx_cpu_get_pc;
-#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &rx_sysemu_ops;
-#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->disas_set_info = rx_cpu_disas_set_info;
diff --git a/target/rx/helper.c b/target/rx/helper.c
index 80912e8dcb4..7f28e729891 100644
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -40,8 +40,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte)
env->psw_c = FIELD_EX32(psw, PSW, C);
}
-#ifndef CONFIG_USER_ONLY
-
#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR)
void rx_cpu_do_interrupt(CPUState *cs)
{
@@ -146,5 +144,3 @@ hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
return addr;
}
-
-#endif /* !CONFIG_USER_ONLY */
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 34/54] target/tricore: Ensure not being build on user emulation
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (32 preceding siblings ...)
2025-03-06 15:47 ` [PULL 33/54] target/rx: Ensure not being build on user emulation Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 35/54] target/mips: Fix possible MSA int overflow Philippe Mathieu-Daudé
` (20 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Currently only system emulation is supported.
Assert no target code is built for user emulation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250121142341.17001-4-philmd@linaro.org>
---
target/tricore/cpu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 8e431d79222..cf9dbc6df8e 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -26,6 +26,10 @@
#include "qemu/cpu-float.h"
#include "tricore-defs.h"
+#ifdef CONFIG_USER_ONLY
+#error "TriCore does not support user mode emulation"
+#endif
+
typedef struct CPUArchState {
/* GPR Register */
uint32_t gpr_a[16];
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 35/54] target/mips: Fix possible MSA int overflow
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (33 preceding siblings ...)
2025-03-06 15:47 ` [PULL 34/54] target/tricore: " Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 36/54] target: Set disassemble_info::endian value for little-endian targets Philippe Mathieu-Daudé
` (19 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
From: Denis Rastyogin <gerben@altlinux.org>
Fix possible overflow in 1 << (DF_BITS(df) - 2) when DF_BITS(df)
is 64 by using a 64-bit integer for the shift operation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Reported-by: Dmitriy Fedin <d.fedin@fobos-nt.ru>
Signed-off-by: Denis Rastyogin <gerben@altlinux.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <20250124122707.54264-1-gerben@altlinux.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/msa_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index ec38d9fde5e..74fb80cc256 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -5577,7 +5577,7 @@ static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int64_t q_min = DF_MIN_INT(df);
int64_t q_max = DF_MAX_INT(df);
- int64_t r_bit = 1 << (DF_BITS(df) - 2);
+ int64_t r_bit = 1LL << (DF_BITS(df) - 2);
if (arg1 == q_min && arg2 == q_min) {
return q_max;
@@ -5685,7 +5685,7 @@ static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t q_max = DF_MAX_INT(df);
int64_t q_min = DF_MIN_INT(df);
- int64_t r_bit = 1 << (DF_BITS(df) - 2);
+ int64_t r_bit = 1LL << (DF_BITS(df) - 2);
q_prod = arg1 * arg2;
q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
@@ -5700,7 +5700,7 @@ static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t q_max = DF_MAX_INT(df);
int64_t q_min = DF_MIN_INT(df);
- int64_t r_bit = 1 << (DF_BITS(df) - 2);
+ int64_t r_bit = 1LL << (DF_BITS(df) - 2);
q_prod = arg1 * arg2;
q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 36/54] target: Set disassemble_info::endian value for little-endian targets
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (34 preceding siblings ...)
2025-03-06 15:47 ` [PULL 35/54] target/mips: Fix possible MSA int overflow Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 37/54] target: Set disassemble_info::endian value for big-endian targets Philippe Mathieu-Daudé
` (18 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field for little-endian targets.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-2-philmd@linaro.org>
---
target/alpha/cpu.c | 1 +
target/avr/cpu.c | 1 +
target/hexagon/cpu.c | 1 +
target/i386/cpu.c | 1 +
target/loongarch/cpu.c | 1 +
target/rx/cpu.c | 1 +
6 files changed, 6 insertions(+)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 57e41fcd784..2eabd7724df 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -85,6 +85,7 @@ static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch)
static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
+ info->endian = BFD_ENDIAN_LITTLE;
info->mach = bfd_mach_alpha_ev6;
info->print_insn = print_insn_alpha;
}
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 5a0e21465e5..2871d30540a 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -102,6 +102,7 @@ static void avr_cpu_reset_hold(Object *obj, ResetType type)
static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
+ info->endian = BFD_ENDIAN_LITTLE;
info->mach = bfd_arch_avr;
info->print_insn = avr_print_insn;
}
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 238e63bcea4..a9beb9a1757 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -293,6 +293,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
info->print_insn = print_insn_hexagon;
+ info->endian = BFD_ENDIAN_LITTLE;
}
static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0cd9b70938d..ab328485acc 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8691,6 +8691,7 @@ static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
+ info->endian = BFD_ENDIAN_LITTLE;
info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
: env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
: bfd_mach_i386_i8086);
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index b4b82425b18..d2e739a029f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -624,6 +624,7 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
+ info->endian = BFD_ENDIAN_LITTLE;
info->print_insn = print_insn_loongarch;
}
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 17ede51cd11..1c40c8977e7 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -168,6 +168,7 @@ static void rx_cpu_set_irq(void *opaque, int no, int request)
static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
+ info->endian = BFD_ENDIAN_LITTLE;
info->mach = bfd_mach_rx;
info->print_insn = print_insn_rx;
}
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 37/54] target: Set disassemble_info::endian value for big-endian targets
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (35 preceding siblings ...)
2025-03-06 15:47 ` [PULL 36/54] target: Set disassemble_info::endian value for little-endian targets Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 38/54] target/arm: Set disassemble_info::endian value in disas_set_info() Philippe Mathieu-Daudé
` (17 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field for big-endian targets.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-3-philmd@linaro.org>
---
target/hppa/cpu.c | 1 +
target/m68k/cpu.c | 1 +
target/openrisc/cpu.c | 1 +
target/s390x/cpu.c | 1 +
target/sparc/cpu.c | 1 +
5 files changed, 5 insertions(+)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 4bb5cff624e..d15f8c9c217 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -150,6 +150,7 @@ static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch)
static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
{
info->mach = bfd_mach_hppa20;
+ info->endian = BFD_ENDIAN_BIG;
info->print_insn = print_insn_hppa;
}
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index eedda07c2ab..df8b9c53fca 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -157,6 +157,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
static void m68k_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
info->print_insn = print_insn_m68k;
+ info->endian = BFD_ENDIAN_BIG;
info->mach = 0;
}
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 785b065b513..e8c357ae836 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -83,6 +83,7 @@ static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch)
static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
{
+ info->endian = BFD_ENDIAN_BIG;
info->print_insn = print_insn_or1k;
}
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 3bea014f9ee..972d265478d 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -243,6 +243,7 @@ static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->mach = bfd_mach_s390_64;
info->cap_arch = CS_ARCH_SYSZ;
+ info->endian = BFD_ENDIAN_BIG;
info->cap_insn_unit = 2;
info->cap_insn_split = 6;
}
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index e3b46137178..9fd222e4c82 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -106,6 +106,7 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->print_insn = print_insn_sparc;
+ info->endian = BFD_ENDIAN_BIG;
#ifdef TARGET_SPARC64
info->mach = bfd_mach_sparc_v9b;
#endif
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 38/54] target/arm: Set disassemble_info::endian value in disas_set_info()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (36 preceding siblings ...)
2025-03-06 15:47 ` [PULL 37/54] target: Set disassemble_info::endian value for big-endian targets Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 39/54] target/microblaze: Set disassemble_info::endian value in disas_set_info Philippe Mathieu-Daudé
` (16 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-4-philmd@linaro.org>
---
target/arm/cpu.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ac1ceec2110..948defa3f5d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1171,7 +1171,7 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
{
ARMCPU *ac = ARM_CPU(cpu);
CPUARMState *env = &ac->env;
- bool sctlr_b;
+ bool sctlr_b = arm_sctlr_b(env);
if (is_a64(env)) {
info->cap_arch = CS_ARCH_ARM64;
@@ -1198,13 +1198,9 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
info->cap_mode = cap_mode;
}
- sctlr_b = arm_sctlr_b(env);
+ info->endian = BFD_ENDIAN_LITTLE;
if (bswap_code(sctlr_b)) {
-#if TARGET_BIG_ENDIAN
- info->endian = BFD_ENDIAN_LITTLE;
-#else
- info->endian = BFD_ENDIAN_BIG;
-#endif
+ info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
}
info->flags &= ~INSN_ARM_BE32;
#ifndef CONFIG_USER_ONLY
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 39/54] target/microblaze: Set disassemble_info::endian value in disas_set_info
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (37 preceding siblings ...)
2025-03-06 15:47 ` [PULL 38/54] target/arm: Set disassemble_info::endian value in disas_set_info() Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 40/54] target/mips: Set disassemble_info::endian value in disas_set_info() Philippe Mathieu-Daudé
` (15 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-5-philmd@linaro.org>
---
target/microblaze/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 13d194cef88..d5ee1244cad 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -224,6 +224,8 @@ static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->mach = bfd_arch_microblaze;
info->print_insn = print_insn_microblaze;
+ info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
+ : BFD_ENDIAN_LITTLE;
}
static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 40/54] target/mips: Set disassemble_info::endian value in disas_set_info()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (38 preceding siblings ...)
2025-03-06 15:47 ` [PULL 39/54] target/microblaze: Set disassemble_info::endian value in disas_set_info Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 41/54] target/ppc: " Philippe Mathieu-Daudé
` (14 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-6-philmd@linaro.org>
---
target/mips/cpu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 0b267d2e507..e76298699ab 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -428,13 +428,13 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) {
-#if TARGET_BIG_ENDIAN
- info->print_insn = print_insn_big_mips;
-#else
- info->print_insn = print_insn_little_mips;
-#endif
+ info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
+ : BFD_ENDIAN_LITTLE;
+ info->print_insn = TARGET_BIG_ENDIAN ? print_insn_big_mips
+ : print_insn_little_mips;
} else {
info->print_insn = print_insn_nanomips;
+ info->endian = BFD_ENDIAN_LITTLE;
}
}
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 41/54] target/ppc: Set disassemble_info::endian value in disas_set_info()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (39 preceding siblings ...)
2025-03-06 15:47 ` [PULL 40/54] target/mips: Set disassemble_info::endian value in disas_set_info() Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 42/54] target/riscv: " Philippe Mathieu-Daudé
` (13 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Have the CPUClass::disas_set_info() callback always set\
the disassemble_info::endian field.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-7-philmd@linaro.org>
---
target/ppc/cpu_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 425049ab093..b9772c53ecc 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7401,6 +7401,8 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
if ((env->hflags >> MSR_LE) & 1) {
info->endian = BFD_ENDIAN_LITTLE;
+ } else {
+ info->endian = BFD_ENDIAN_BIG;
}
info->mach = env->bfd_mach;
if (!env->bfd_mach) {
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 42/54] target/riscv: Set disassemble_info::endian value in disas_set_info()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (40 preceding siblings ...)
2025-03-06 15:47 ` [PULL 41/54] target/ppc: " Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 43/54] target/sh4: " Philippe Mathieu-Daudé
` (12 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-8-philmd@linaro.org>
---
target/riscv/cpu.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 47424fd5e2a..6da391738f3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1152,6 +1152,15 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
CPURISCVState *env = &cpu->env;
info->target_info = &cpu->cfg;
+ /*
+ * A couple of bits in MSTATUS set the endianness:
+ * - MSTATUS_UBE (User-mode),
+ * - MSTATUS_SBE (Supervisor-mode),
+ * - MSTATUS_MBE (Machine-mode)
+ * but we don't implement that yet.
+ */
+ info->endian = BFD_ENDIAN_LITTLE;
+
switch (env->xl) {
case MXL_RV32:
info->print_insn = print_insn_riscv32;
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 43/54] target/sh4: Set disassemble_info::endian value in disas_set_info()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (41 preceding siblings ...)
2025-03-06 15:47 ` [PULL 42/54] target/riscv: " Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 44/54] target/xtensa: " Philippe Mathieu-Daudé
` (11 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-9-philmd@linaro.org>
---
target/sh4/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 22cdf9b4e12..c2aaa40a037 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -143,6 +143,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
+ info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
+ : BFD_ENDIAN_LITTLE;
info->mach = bfd_mach_sh4;
info->print_insn = print_insn_sh;
}
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 44/54] target/xtensa: Set disassemble_info::endian value in disas_set_info()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (42 preceding siblings ...)
2025-03-06 15:47 ` [PULL 43/54] target/sh4: " Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 45/54] disas: Remove target_words_bigendian() call in initialize_debug_target() Philippe Mathieu-Daudé
` (10 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-10-philmd@linaro.org>
---
target/xtensa/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index efbfe73fcfb..f9e298ace45 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -159,6 +159,8 @@ static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
info->private_data = cpu->env.config->isa;
info->print_insn = print_insn_xtensa;
+ info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
+ : BFD_ENDIAN_LITTLE;
}
static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 45/54] disas: Remove target_words_bigendian() call in initialize_debug_target()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (43 preceding siblings ...)
2025-03-06 15:47 ` [PULL 44/54] target/xtensa: " Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 46/54] target/i386: Constify X86CPUModel uses Philippe Mathieu-Daudé
` (9 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
All CPUClass implementating disas_set_info() must set the
disassemble_info::endian value.
Ensure that by setting %endian to BFD_ENDIAN_UNKNOWN before
calling the CPUClass::disas_set_info() handler, then asserting
%endian is not BFD_ENDIAN_UNKNOWN after the call.
This allows removing the target_words_bigendian() call in disas/.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20250210212931.62401-11-philmd@linaro.org>
---
disas/disas-common.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/disas/disas-common.c b/disas/disas-common.c
index de61f6d8a12..ae3f9e46ea1 100644
--- a/disas/disas-common.c
+++ b/disas/disas-common.c
@@ -7,7 +7,6 @@
#include "disas/disas.h"
#include "disas/capstone.h"
#include "hw/core/cpu.h"
-#include "exec/tswap.h"
#include "disas-internal.h"
@@ -61,15 +60,12 @@ void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu)
s->cpu = cpu;
s->info.print_address_func = print_address;
- if (target_words_bigendian()) {
- s->info.endian = BFD_ENDIAN_BIG;
- } else {
- s->info.endian = BFD_ENDIAN_LITTLE;
- }
+ s->info.endian = BFD_ENDIAN_UNKNOWN;
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->disas_set_info) {
cc->disas_set_info(cpu, &s->info);
+ g_assert(s->info.endian != BFD_ENDIAN_UNKNOWN);
}
}
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 46/54] target/i386: Constify X86CPUModel uses
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (44 preceding siblings ...)
2025-03-06 15:47 ` [PULL 45/54] disas: Remove target_words_bigendian() call in initialize_debug_target() Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 47/54] target/sparc: Constify SPARCCPUClass::cpu_def Philippe Mathieu-Daudé
` (8 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210133134.90879-2-philmd@linaro.org>
---
target/i386/cpu.h | 2 +-
target/i386/cpu.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 10ce019e3f8..7882b63b9b6 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2327,7 +2327,7 @@ struct X86CPUClass {
* CPU definition, automatically loaded by instance_init if not NULL.
* Should be eventually replaced by subclass-specific property defaults.
*/
- X86CPUModel *model;
+ const X86CPUModel *model;
bool host_cpuid_required;
int ordering;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ab328485acc..b3e1c2bca49 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6563,7 +6563,7 @@ void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
* Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
*/
-static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
+static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model)
{
const X86CPUVersionDefinition *vdef;
X86CPUVersion version = x86_cpu_model_resolve_version(model);
@@ -6592,7 +6592,7 @@ static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
}
static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu,
- X86CPUModel *model)
+ const X86CPUModel *model)
{
const X86CPUVersionDefinition *vdef;
X86CPUVersion version = x86_cpu_model_resolve_version(model);
@@ -6620,7 +6620,7 @@ static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu,
* Load data from X86CPUDefinition into a X86CPU object.
* Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
*/
-static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
+static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model)
{
const X86CPUDefinition *def = model->cpudef;
CPUX86State *env = &cpu->env;
@@ -6690,7 +6690,7 @@ static const gchar *x86_gdb_arch_name(CPUState *cs)
static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
{
- X86CPUModel *model = data;
+ const X86CPUModel *model = data;
X86CPUClass *xcc = X86_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 47/54] target/sparc: Constify SPARCCPUClass::cpu_def
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (45 preceding siblings ...)
2025-03-06 15:47 ` [PULL 46/54] target/i386: Constify X86CPUModel uses Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 48/54] target/xtensa: Finalize config in xtensa_register_core() Philippe Mathieu-Daudé
` (7 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210133134.90879-3-philmd@linaro.org>
---
target/sparc/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index dda811503b5..462bcb6c0e6 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -574,7 +574,7 @@ struct SPARCCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
- sparc_def_t *cpu_def;
+ const sparc_def_t *cpu_def;
};
#ifndef CONFIG_USER_ONLY
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 48/54] target/xtensa: Finalize config in xtensa_register_core()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (46 preceding siblings ...)
2025-03-06 15:47 ` [PULL 47/54] target/sparc: Constify SPARCCPUClass::cpu_def Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 49/54] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Philippe Mathieu-Daudé
` (6 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Make XtensaConfigList::config not const. Only modify
XtensaConfig within xtensa_register_core(), when the
class is registered, not when it is initialized.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Message-Id: <20250210133134.90879-4-philmd@linaro.org>
---
target/xtensa/cpu.h | 2 +-
target/xtensa/helper.c | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 0e6302c5bd3..8d70bfc0cd4 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -490,7 +490,7 @@ typedef struct XtensaConfig {
} XtensaConfig;
typedef struct XtensaConfigList {
- const XtensaConfig *config;
+ XtensaConfig *config;
struct XtensaConfigList *next;
} XtensaConfigList;
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index 2978c471c1f..f64699b116d 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -173,9 +173,8 @@ static void xtensa_core_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
- XtensaConfig *config = data;
+ const XtensaConfig *config = data;
- xtensa_finalize_config(config);
xcc->config = config;
/*
@@ -195,6 +194,8 @@ void xtensa_register_core(XtensaConfigList *node)
.class_data = (void *)node->config,
};
+ xtensa_finalize_config(node->config);
+
node->next = xtensa_cores;
xtensa_cores = node;
type.name = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), node->config->name);
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 49/54] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (47 preceding siblings ...)
2025-03-06 15:47 ` [PULL 48/54] target/xtensa: Finalize config in xtensa_register_core() Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 50/54] target/riscv: Convert misa_mxl_max using GLib macros Philippe Mathieu-Daudé
` (5 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210133134.90879-5-philmd@linaro.org>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 616c3bdc1c2..7de19b41836 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -539,7 +539,7 @@ struct RISCVCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
- uint32_t misa_mxl_max; /* max mxl for this cpu */
+ RISCVMXL misa_mxl_max; /* max mxl for this cpu */
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6da391738f3..d4f01965dfa 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3056,7 +3056,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
- mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
+ mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
riscv_cpu_validate_misa_mxl(mcc);
}
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 50/54] target/riscv: Convert misa_mxl_max using GLib macros
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (48 preceding siblings ...)
2025-03-06 15:47 ` [PULL 49/54] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 51/54] target/alpha: Do not mix exception flags and FPCR bits Philippe Mathieu-Daudé
` (4 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Use GLib conversion macros to pass misa_mxl_max as
riscv_cpu_class_init() class data.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210133134.90879-6-philmd@linaro.org>
---
target/riscv/cpu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d4f01965dfa..6db2252aac7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3056,7 +3056,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
- mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
+ mcc->misa_mxl_max = (RISCVMXL)GPOINTER_TO_UINT(data);
riscv_cpu_validate_misa_mxl(mcc);
}
@@ -3158,7 +3158,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_DYNAMIC_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \
@@ -3167,7 +3167,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_VENDOR_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \
@@ -3176,7 +3176,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
@@ -3185,7 +3185,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
static const TypeInfo riscv_cpu_type_infos[] = {
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 51/54] target/alpha: Do not mix exception flags and FPCR bits
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (49 preceding siblings ...)
2025-03-06 15:47 ` [PULL 50/54] target/riscv: Convert misa_mxl_max using GLib macros Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 52/54] target/i386: Mark WHPX APIC region as little-endian Philippe Mathieu-Daudé
` (3 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
get_float_exception_flags() returns exception flags,
which are distinct from the FPCR bits used as error code.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250211162604.83446-1-philmd@linaro.org>
---
target/alpha/fpu_helper.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c
index f810a9b6a47..6aefb9b851a 100644
--- a/target/alpha/fpu_helper.c
+++ b/target/alpha/fpu_helper.c
@@ -455,29 +455,28 @@ static uint64_t do_cvttq(CPUAlphaState *env, uint64_t a, int roundmode)
{
float64 fa;
int64_t ret;
- uint32_t exc;
+ uint32_t exc = 0;
+ int flags;
fa = t_to_float64(a);
ret = float64_to_int64_modulo(fa, roundmode, &FP_STATUS);
- exc = get_float_exception_flags(&FP_STATUS);
- if (unlikely(exc)) {
+ flags = get_float_exception_flags(&FP_STATUS);
+ if (unlikely(flags)) {
set_float_exception_flags(0, &FP_STATUS);
/* We need to massage the resulting exceptions. */
- if (exc & float_flag_invalid_cvti) {
+ if (flags & float_flag_invalid_cvti) {
/* Overflow, either normal or infinity. */
if (float64_is_infinity(fa)) {
exc = FPCR_INV;
} else {
exc = FPCR_IOV | FPCR_INE;
}
- } else if (exc & float_flag_invalid) {
+ } else if (flags & float_flag_invalid) {
exc = FPCR_INV;
- } else if (exc & float_flag_inexact) {
+ } else if (flags & float_flag_inexact) {
exc = FPCR_INE;
- } else {
- exc = 0;
}
}
env->error_code = exc;
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 52/54] target/i386: Mark WHPX APIC region as little-endian
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (50 preceding siblings ...)
2025-03-06 15:47 ` [PULL 51/54] target/alpha: Do not mix exception flags and FPCR bits Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 53/54] system: Open-code qemu_init_arch_modules() using target_name() Philippe Mathieu-Daudé
` (2 subsequent siblings)
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
This device is only used by the x86 targets, which are only
built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN
definition expand to DEVICE_LITTLE_ENDIAN (besides, the
DEVICE_BIG_ENDIAN case isn't tested). Simplify directly
using DEVICE_LITTLE_ENDIAN.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250212113938.38692-6-philmd@linaro.org>
---
target/i386/whpx/whpx-apic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c
index 4245ab68a27..630a9616d71 100644
--- a/target/i386/whpx/whpx-apic.c
+++ b/target/i386/whpx/whpx-apic.c
@@ -231,7 +231,7 @@ static void whpx_apic_mem_write(void *opaque, hwaddr addr,
static const MemoryRegionOps whpx_apic_io_ops = {
.read = whpx_apic_mem_read,
.write = whpx_apic_mem_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void whpx_apic_reset(APICCommonState *s)
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 53/54] system: Open-code qemu_init_arch_modules() using target_name()
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (51 preceding siblings ...)
2025-03-06 15:47 ` [PULL 52/54] target/i386: Mark WHPX APIC region as little-endian Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 54/54] include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition Philippe Mathieu-Daudé
2025-03-07 7:18 ` [PULL 00/54] Accelerators & CPU patches Stefan Hajnoczi
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Mostly revert commit c80cafa0c73 ("system: Add qemu_init_arch_modules")
but using target_name() instead of the target specific 'TARGET_NAME'
definition.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250305005225.95051-3-philmd@linaro.org>
---
include/system/arch_init.h | 2 --
system/arch_init.c | 9 ---------
system/vl.c | 7 ++++++-
3 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/include/system/arch_init.h b/include/system/arch_init.h
index 5b1c1026f3a..d8b77440487 100644
--- a/include/system/arch_init.h
+++ b/include/system/arch_init.h
@@ -27,6 +27,4 @@ enum {
extern const uint32_t arch_type;
-void qemu_init_arch_modules(void);
-
#endif
diff --git a/system/arch_init.c b/system/arch_init.c
index d2c32f84887..b1baed18a30 100644
--- a/system/arch_init.c
+++ b/system/arch_init.c
@@ -22,7 +22,6 @@
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
-#include "qemu/module.h"
#include "system/arch_init.h"
#ifdef TARGET_SPARC
@@ -40,11 +39,3 @@ int graphic_depth = 32;
#endif
const uint32_t arch_type = QEMU_ARCH;
-
-void qemu_init_arch_modules(void)
-{
-#ifdef CONFIG_MODULES
- module_init_info(qemu_modinfo);
- module_allow_arch(TARGET_NAME);
-#endif
-}
diff --git a/system/vl.c b/system/vl.c
index 8f776684ec8..04f78466c41 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -26,6 +26,7 @@
#include "qemu/help-texts.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
+#include "qemu/module.h"
#include "exec/cpu-common.h"
#include "exec/page-vary.h"
#include "hw/qdev-properties.h"
@@ -78,6 +79,7 @@
#include "hw/block/block.h"
#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
+#include "hw/core/cpu.h"
#include "migration/cpr.h"
#include "migration/misc.h"
#include "migration/snapshot.h"
@@ -2885,7 +2887,10 @@ void qemu_init(int argc, char **argv)
os_setup_limits();
- qemu_init_arch_modules();
+#ifdef CONFIG_MODULES
+ module_init_info(qemu_modinfo);
+ module_allow_arch(target_name());
+#endif
qemu_init_subsystems();
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PULL 54/54] include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (52 preceding siblings ...)
2025-03-06 15:47 ` [PULL 53/54] system: Open-code qemu_init_arch_modules() using target_name() Philippe Mathieu-Daudé
@ 2025-03-06 15:47 ` Philippe Mathieu-Daudé
2025-03-07 7:18 ` [PULL 00/54] Accelerators & CPU patches Stefan Hajnoczi
54 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-03-06 15:47 UTC (permalink / raw)
To: qemu-devel
Ensure common code never use this target specific definition.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250305153929.43687-4-philmd@linaro.org>
---
include/exec/poison.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/poison.h b/include/exec/poison.h
index f4283f693af..d6d4832854e 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -48,6 +48,7 @@
#pragma GCC poison TARGET_PAGE_MASK
#pragma GCC poison TARGET_PAGE_BITS
#pragma GCC poison TARGET_PAGE_ALIGN
+#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS
#pragma GCC poison CPU_INTERRUPT_HARD
#pragma GCC poison CPU_INTERRUPT_EXITTB
--
2.47.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PULL 00/54] Accelerators & CPU patches
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
` (53 preceding siblings ...)
2025-03-06 15:47 ` [PULL 54/54] include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition Philippe Mathieu-Daudé
@ 2025-03-07 7:18 ` Stefan Hajnoczi
54 siblings, 0 replies; 56+ messages in thread
From: Stefan Hajnoczi @ 2025-03-07 7:18 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread