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From: Conor Dooley <conor@kernel.org>
To: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Min Lin <linmin@eswincomputing.com>,
	Pritesh Patel <pritesh.patel@einfochips.com>,
	Yangyu Chen <cyy@cyyself.name>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Yu Chien Peter Lin <peterlin@andestech.com>,
	Charlie Jenkins <charlie@rivosinc.com>,
	Kanak Shilledar <kanakshilledar@gmail.com>,
	Darshan Prajapati <darshan.prajapati@einfochips.com>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Aradhya Bhatia <a-bhatia1@ti.com>,
	rafal@milecki.pl, Anup Patel <anup@brainfault.org>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 02/10] riscv: Add Kconfig option for ESWIN platforms
Date: Tue, 11 Mar 2025 18:14:53 +0000	[thread overview]
Message-ID: <20250311-cache-trance-c47cf760b587@spud> (raw)
In-Reply-To: <20250311073432.4068512-3-pinkesh.vaghela@einfochips.com>


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On Tue, Mar 11, 2025 at 01:04:24PM +0530, Pinkesh Vaghela wrote:
> Create a config option to build ESWIN SoC specific resources
> 
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> ---
>  arch/riscv/Kconfig.socs | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 1916cf7ba450..35594e365ca6 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -1,5 +1,11 @@
>  menu "SoC selection"
>  
> +config ARCH_ESWIN
> +	bool "ESWIN SoCs"
> +	help
> +	  This enables support for ESWIN SoC platform hardware,
> +	  including the ESWIN EIC7700 SoC.
> +
>  config ARCH_MICROCHIP_POLARFIRE
>  	def_bool ARCH_MICROCHIP
>  
> -- 
> 2.25.1
> 

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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Min Lin <linmin@eswincomputing.com>,
	Pritesh Patel <pritesh.patel@einfochips.com>,
	Yangyu Chen <cyy@cyyself.name>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Yu Chien Peter Lin <peterlin@andestech.com>,
	Charlie Jenkins <charlie@rivosinc.com>,
	Kanak Shilledar <kanakshilledar@gmail.com>,
	Darshan Prajapati <darshan.prajapati@einfochips.com>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Aradhya Bhatia <a-bhatia1@ti.com>,
	rafal@milecki.pl, Anup Patel <anup@brainfault.org>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 02/10] riscv: Add Kconfig option for ESWIN platforms
Date: Tue, 11 Mar 2025 18:14:53 +0000	[thread overview]
Message-ID: <20250311-cache-trance-c47cf760b587@spud> (raw)
In-Reply-To: <20250311073432.4068512-3-pinkesh.vaghela@einfochips.com>

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On Tue, Mar 11, 2025 at 01:04:24PM +0530, Pinkesh Vaghela wrote:
> Create a config option to build ESWIN SoC specific resources
> 
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> ---
>  arch/riscv/Kconfig.socs | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 1916cf7ba450..35594e365ca6 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -1,5 +1,11 @@
>  menu "SoC selection"
>  
> +config ARCH_ESWIN
> +	bool "ESWIN SoCs"
> +	help
> +	  This enables support for ESWIN SoC platform hardware,
> +	  including the ESWIN EIC7700 SoC.
> +
>  config ARCH_MICROCHIP_POLARFIRE
>  	def_bool ARCH_MICROCHIP
>  
> -- 
> 2.25.1
> 

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  reply	other threads:[~2025-03-11 18:35 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-11  7:34 [PATCH 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC Pinkesh Vaghela
2025-03-11  7:34 ` Pinkesh Vaghela
2025-03-11  7:34 ` [PATCH 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible Pinkesh Vaghela
2025-03-11  7:34   ` Pinkesh Vaghela
2025-03-11 18:14   ` Conor Dooley
2025-03-11 18:14     ` Conor Dooley
2025-03-11  7:34 ` [PATCH 02/10] riscv: Add Kconfig option for ESWIN platforms Pinkesh Vaghela
2025-03-11  7:34   ` Pinkesh Vaghela
2025-03-11 18:14   ` Conor Dooley [this message]
2025-03-11 18:14     ` Conor Dooley
2025-03-11  7:34 ` [PATCH 03/10] dt-bindings: vendor-prefixes: add eswin Pinkesh Vaghela
2025-03-11  7:34   ` Pinkesh Vaghela
2025-03-11 18:15   ` Conor Dooley
2025-03-11 18:15     ` Conor Dooley
2025-03-11  7:34 ` [PATCH 04/10] dt-bindings: riscv: Add SiFive HiFive Premier P550 board Pinkesh Vaghela
2025-03-11  7:34   ` Pinkesh Vaghela
2025-03-12 12:03   ` Matthias Brugger
2025-03-12 12:03     ` Matthias Brugger
2025-03-12 12:50     ` Conor Dooley
2025-03-12 12:50       ` Conor Dooley
2025-03-12 12:52       ` Matthias Brugger
2025-03-12 12:52         ` Matthias Brugger
2025-03-12 12:55   ` Krzysztof Kozlowski
2025-03-12 12:55     ` Krzysztof Kozlowski
2025-03-12 14:25     ` [External] " Pinkesh Vaghela
2025-03-12 14:25       ` Pinkesh Vaghela
2025-03-13  8:15     ` Samuel Holland
2025-03-13  8:15       ` Samuel Holland
2025-03-13  8:39       ` Krzysztof Kozlowski
2025-03-13  8:39         ` Krzysztof Kozlowski
2025-03-11  7:34 ` [PATCH 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility Pinkesh Vaghela
2025-03-11  7:34   ` Pinkesh Vaghela
2025-03-11 18:11   ` Conor Dooley
2025-03-11 18:11     ` Conor Dooley
2025-03-12 13:51     ` [External] " Pinkesh Vaghela
2025-03-12 13:51       ` Pinkesh Vaghela
2025-03-11  7:34 ` [PATCH 06/10] cache: sifive_ccache: Add ESWIN EIC7700 support Pinkesh Vaghela
2025-03-11  7:34   ` Pinkesh Vaghela
2025-03-11  7:34 ` [PATCH 07/10] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC Pinkesh Vaghela
2025-03-11  7:34   ` Pinkesh Vaghela
2025-03-11 18:12   ` Conor Dooley
2025-03-11 18:12     ` Conor Dooley
2025-03-11  7:34 ` [PATCH 08/10] dt-bindings: timer: Add ESWIN EIC7700 CLINT Pinkesh Vaghela
2025-03-11  7:34   ` Pinkesh Vaghela
2025-03-11 18:12   ` Conor Dooley
2025-03-11 18:12     ` Conor Dooley
2025-03-11  7:34 ` [PATCH 09/10] riscv: dts: add initial support for EIC7700 SoC Pinkesh Vaghela
2025-03-11  7:34   ` Pinkesh Vaghela
2025-03-11  7:34 ` [PATCH 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree Pinkesh Vaghela
2025-03-11  7:34   ` Pinkesh Vaghela
2025-03-11 18:07 ` [PATCH 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC Conor Dooley
2025-03-11 18:07   ` Conor Dooley
2025-03-20 10:39   ` Pinkesh Vaghela
2025-03-20 10:39     ` Pinkesh Vaghela
2025-03-20 12:00     ` Conor Dooley
2025-03-20 12:00       ` Conor Dooley
2025-03-21  9:37       ` Krzysztof Kozlowski
2025-03-21  9:37         ` Krzysztof Kozlowski
2025-03-21 11:29         ` Pinkesh Vaghela
2025-03-21 11:29           ` Pinkesh Vaghela
2025-03-21 13:41           ` Conor Dooley
2025-03-21 13:41             ` Conor Dooley
2025-03-21 11:25       ` Pinkesh Vaghela
2025-03-21 11:25         ` Pinkesh Vaghela

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