From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
qemu-ppc@nongnu.org, Chalapathi V <chalapathi.v@linux.ibm.com>
Subject: [PULL 38/72] hw/ssi/pnv_spi: Use local var seq_index instead of get_seq_index().
Date: Tue, 11 Mar 2025 22:57:32 +1000 [thread overview]
Message-ID: <20250311125815.903177-39-npiggin@gmail.com> (raw)
In-Reply-To: <20250311125815.903177-1-npiggin@gmail.com>
From: Chalapathi V <chalapathi.v@linux.ibm.com>
Use a local variable seq_index instead of repeatedly calling
get_seq_index() method and open-code next_sequencer_fsm().
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20250303141328.23991-3-chalapathi.v@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ssi/pnv_spi.c | 97 ++++++++++++++++++++++++++----------------------
1 file changed, 52 insertions(+), 45 deletions(-)
diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c
index 388b425157..de33542c35 100644
--- a/hw/ssi/pnv_spi.c
+++ b/hw/ssi/pnv_spi.c
@@ -227,18 +227,6 @@ static void transfer(PnvSpi *s)
fifo8_reset(&s->rx_fifo);
}
-static inline uint8_t get_seq_index(PnvSpi *s)
-{
- return GETFIELD(SPI_STS_SEQ_INDEX, s->status);
-}
-
-static inline void next_sequencer_fsm(PnvSpi *s)
-{
- uint8_t seq_index = get_seq_index(s);
- s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, (seq_index + 1));
- s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_INDEX_INCREMENT);
-}
-
/*
* Calculate the N1 counters based on passed in opcode and
* internal register values.
@@ -664,6 +652,7 @@ static void operation_sequencer(PnvSpi *s)
bool stop = false; /* Flag to stop the sequencer */
uint8_t opcode = 0;
uint8_t masked_opcode = 0;
+ uint8_t seq_index;
/*
* Clear the sequencer FSM error bit - general_SPI_status[3]
@@ -677,12 +666,17 @@ static void operation_sequencer(PnvSpi *s)
if (GETFIELD(SPI_STS_SEQ_FSM, s->status) == SEQ_STATE_IDLE) {
s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0);
}
+ /*
+ * SPI_STS_SEQ_INDEX of status register is kept in seq_index variable and
+ * updated back to status register at the end of operation_sequencer().
+ */
+ seq_index = GETFIELD(SPI_STS_SEQ_INDEX, s->status);
/*
* There are only 8 possible operation IDs to iterate through though
* some operations may cause more than one frame to be sequenced.
*/
- while (get_seq_index(s) < NUM_SEQ_OPS) {
- opcode = s->seq_op[get_seq_index(s)];
+ while (seq_index < NUM_SEQ_OPS) {
+ opcode = s->seq_op[seq_index];
/* Set sequencer state to decode */
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_DECODE);
/*
@@ -699,7 +693,7 @@ static void operation_sequencer(PnvSpi *s)
case SEQ_OP_STOP:
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE);
/* A stop operation in any position stops the sequencer */
- trace_pnv_spi_sequencer_op("STOP", get_seq_index(s));
+ trace_pnv_spi_sequencer_op("STOP", seq_index);
stop = true;
s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE);
@@ -710,7 +704,7 @@ static void operation_sequencer(PnvSpi *s)
case SEQ_OP_SELECT_SLAVE:
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE);
- trace_pnv_spi_sequencer_op("SELECT_SLAVE", get_seq_index(s));
+ trace_pnv_spi_sequencer_op("SELECT_SLAVE", seq_index);
/*
* This device currently only supports a single responder
* connection at position 0. De-selecting a responder is fine
@@ -721,8 +715,7 @@ static void operation_sequencer(PnvSpi *s)
if (s->responder_select == 0) {
trace_pnv_spi_shifter_done();
qemu_set_irq(s->cs_line[0], 1);
- s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status,
- (get_seq_index(s) + 1));
+ seq_index++;
s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_DONE);
} else if (s->responder_select != 1) {
qemu_log_mask(LOG_GUEST_ERROR, "Slave selection other than 1 "
@@ -747,13 +740,15 @@ static void operation_sequencer(PnvSpi *s)
* applies once a valid responder select has occurred.
*/
s->shift_n1_done = false;
- next_sequencer_fsm(s);
+ seq_index++;
+ s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status,
+ SEQ_STATE_INDEX_INCREMENT);
}
break;
case SEQ_OP_SHIFT_N1:
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE);
- trace_pnv_spi_sequencer_op("SHIFT_N1", get_seq_index(s));
+ trace_pnv_spi_sequencer_op("SHIFT_N1", seq_index);
/*
* Only allow a shift_n1 when the state is not IDLE or DONE.
* In either of those two cases the sequencer is not in a proper
@@ -785,8 +780,9 @@ static void operation_sequencer(PnvSpi *s)
* transmission to the responder without requiring a refill of
* the TDR between the two operations.
*/
- if (PNV_SPI_MASKED_OPCODE(s->seq_op[get_seq_index(s) + 1])
- == SEQ_OP_SHIFT_N2) {
+ if ((seq_index != 7) &&
+ PNV_SPI_MASKED_OPCODE(s->seq_op[(seq_index + 1)]) ==
+ SEQ_OP_SHIFT_N2) {
send_n1_alone = false;
}
s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_SHIFT_N1);
@@ -806,9 +802,8 @@ static void operation_sequencer(PnvSpi *s)
if (GETFIELD(SPI_STS_TDR_UNDERRUN, s->status)) {
s->shift_n1_done = true;
s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status,
- FSM_SHIFT_N2);
- s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status,
- (get_seq_index(s) + 1));
+ FSM_SHIFT_N2);
+ seq_index++;
} else {
/*
* This is case (1) or (2) so the sequencer needs to
@@ -819,14 +814,16 @@ static void operation_sequencer(PnvSpi *s)
} else {
/* Ok to move on to the next index */
s->shift_n1_done = true;
- next_sequencer_fsm(s);
+ seq_index++;
+ s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status,
+ SEQ_STATE_INDEX_INCREMENT);
}
}
break;
case SEQ_OP_SHIFT_N2:
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE);
- trace_pnv_spi_sequencer_op("SHIFT_N2", get_seq_index(s));
+ trace_pnv_spi_sequencer_op("SHIFT_N2", seq_index);
if (!s->shift_n1_done) {
qemu_log_mask(LOG_GUEST_ERROR, "Shift_N2 is not allowed if a "
"Shift_N1 is not done, shifter state = 0x%llx",
@@ -851,14 +848,16 @@ static void operation_sequencer(PnvSpi *s)
s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_WAIT);
} else {
/* Ok to move on to the next index */
- next_sequencer_fsm(s);
+ seq_index++;
+ s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status,
+ SEQ_STATE_INDEX_INCREMENT);
}
}
break;
case SEQ_OP_BRANCH_IFNEQ_RDR:
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE);
- trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_RDR", get_seq_index(s));
+ trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_RDR", seq_index);
/*
* The memory mapping register RDR match value is compared against
* the 16 rightmost bytes of the RDR (potentially with masking).
@@ -874,15 +873,16 @@ static void operation_sequencer(PnvSpi *s)
if (rdr_matched) {
trace_pnv_spi_RDR_match("success");
/* A match occurred, increment the sequencer index. */
- next_sequencer_fsm(s);
+ seq_index++;
+ s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status,
+ SEQ_STATE_INDEX_INCREMENT);
} else {
trace_pnv_spi_RDR_match("failed");
/*
* Branch the sequencer to the index coded into the op
* code.
*/
- s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status,
- PNV_SPI_OPCODE_LO_NIBBLE(opcode));
+ seq_index = PNV_SPI_OPCODE_LO_NIBBLE(opcode);
}
/*
* Regardless of where the branch ended up we want the
@@ -901,12 +901,13 @@ static void operation_sequencer(PnvSpi *s)
case SEQ_OP_TRANSFER_TDR:
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE);
qemu_log_mask(LOG_GUEST_ERROR, "Transfer TDR is not supported\n");
- next_sequencer_fsm(s);
+ seq_index++;
+ s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_INDEX_INCREMENT);
break;
case SEQ_OP_BRANCH_IFNEQ_INC_1:
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE);
- trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_1", get_seq_index(s));
+ trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_1", seq_index);
/*
* The spec says the loop should execute count compare + 1 times.
* However we learned from engineering that we really only loop
@@ -920,19 +921,21 @@ static void operation_sequencer(PnvSpi *s)
* mask off all but the first three bits so we don't try to
* access beyond the sequencer_operation_reg boundary.
*/
- s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status,
- PNV_SPI_OPCODE_LO_NIBBLE(opcode));
+ seq_index = PNV_SPI_OPCODE_LO_NIBBLE(opcode);
s->loop_counter_1++;
} else {
/* Continue to next index if loop counter is reached */
- next_sequencer_fsm(s);
+ seq_index++;
+ s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status,
+ SEQ_STATE_INDEX_INCREMENT);
}
break;
case SEQ_OP_BRANCH_IFNEQ_INC_2:
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE);
- trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_2", get_seq_index(s));
- uint8_t condition2 = GETFIELD(SPI_CTR_CFG_CMP2, s->regs[SPI_CTR_CFG_REG]);
+ trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_2", seq_index);
+ uint8_t condition2 = GETFIELD(SPI_CTR_CFG_CMP2,
+ s->regs[SPI_CTR_CFG_REG]);
/*
* The spec says the loop should execute count compare + 1 times.
* However we learned from engineering that we really only loop
@@ -945,19 +948,21 @@ static void operation_sequencer(PnvSpi *s)
* mask off all but the first three bits so we don't try to
* access beyond the sequencer_operation_reg boundary.
*/
- s->status = SETFIELD(SPI_STS_SEQ_INDEX,
- s->status, PNV_SPI_OPCODE_LO_NIBBLE(opcode));
+ seq_index = PNV_SPI_OPCODE_LO_NIBBLE(opcode);
s->loop_counter_2++;
} else {
/* Continue to next index if loop counter is reached */
- next_sequencer_fsm(s);
+ seq_index++;
+ s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status,
+ SEQ_STATE_INDEX_INCREMENT);
}
break;
default:
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE);
/* Ignore unsupported operations. */
- next_sequencer_fsm(s);
+ seq_index++;
+ s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_INDEX_INCREMENT);
break;
} /* end of switch */
/*
@@ -965,10 +970,10 @@ static void operation_sequencer(PnvSpi *s)
* we need to go ahead and end things as if there was a STOP at the
* end.
*/
- if (get_seq_index(s) == NUM_SEQ_OPS) {
+ if (seq_index == NUM_SEQ_OPS) {
/* All 8 opcodes completed, sequencer idling */
s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE);
- s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0);
+ seq_index = 0;
s->loop_counter_1 = 0;
s->loop_counter_2 = 0;
s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_IDLE);
@@ -979,6 +984,8 @@ static void operation_sequencer(PnvSpi *s)
break;
}
} /* end of while */
+ /* Update sequencer index field in status.*/
+ s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, seq_index);
return;
} /* end of operation_sequencer() */
--
2.47.1
next prev parent reply other threads:[~2025-03-11 13:12 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-11 12:56 [PULL 00/72] ppc-for-10.0-1 queue Nicholas Piggin
2025-03-11 12:56 ` [PULL 01/72] ppc/ppc405: Remove tests Nicholas Piggin
2025-03-11 12:56 ` [PULL 02/72] ppc/ppc405: Remove boards Nicholas Piggin
2025-03-11 12:56 ` [PULL 03/72] hw/ppc: Deprecate 405 CPUs Nicholas Piggin
2025-03-11 12:56 ` [PULL 04/72] ppc/pnv: Update skiboot to 7.1-106 Nicholas Piggin
2025-03-11 12:56 ` [PULL 05/72] pseries: Update SLOF firmware image Nicholas Piggin
2025-03-11 12:57 ` [PULL 06/72] ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5 Nicholas Piggin
2025-03-11 12:57 ` [PULL 07/72] ppc/pnv/homer: Fix OCC registers Nicholas Piggin
2025-03-11 12:57 ` [PULL 08/72] ppc/pnv/homer: Make dummy reads return 0 Nicholas Piggin
2025-03-11 12:57 ` [PULL 09/72] ppc/pnv/occ: Fix common area sensor offsets Nicholas Piggin
2025-03-13 7:57 ` Michael Tokarev
2025-03-11 12:57 ` [PULL 10/72] ppc/pnv/homer: class-based base and size Nicholas Piggin
2025-03-11 12:57 ` [PULL 11/72] ppc/pnv/occ: Better document OCCMISC bits Nicholas Piggin
2025-03-11 12:57 ` [PULL 12/72] ppc/pnv: Make HOMER memory a RAM region Nicholas Piggin
2025-03-11 12:57 ` [PULL 13/72] ppc/pnv/occ: Update pstate frequency tables Nicholas Piggin
2025-03-11 12:57 ` [PULL 14/72] ppc/pnv/occ: Add POWER10 OCC-OPAL data format Nicholas Piggin
2025-03-11 12:57 ` [PULL 15/72] ppc/pnv/occ: Implement a basic dynamic OCC model Nicholas Piggin
2025-03-11 12:57 ` [PULL 16/72] target/ppc: Add Power9/10 power management SPRs Nicholas Piggin
2025-03-11 12:57 ` [PULL 17/72] ppc/pnv: Support LPC host controller irqs other than serirqs Nicholas Piggin
2025-03-11 12:57 ` [PULL 18/72] ppc/pnv: raise no-response errors if an LPC transaction fails Nicholas Piggin
2025-03-11 12:57 ` [PULL 19/72] ppc/pnv: Implement LPC FW address space IDSEL Nicholas Piggin
2025-03-11 12:57 ` [PULL 20/72] ppc/pnv: Move PNOR to offset 0 in the ISA FW space Nicholas Piggin
2025-03-11 12:57 ` [PULL 21/72] ppc/pnv: Add a PNOR address and size sanity checks Nicholas Piggin
2025-03-11 12:57 ` [PULL 22/72] ppc/pnv: Add a default formatted PNOR image Nicholas Piggin
2025-03-11 12:57 ` [PULL 23/72] ppc/xive2: Update NVP save/restore for group attributes Nicholas Piggin
2025-03-11 12:57 ` [PULL 24/72] ppc/xive: Rename ipb_to_pipr() to xive_ipb_to_pipr() Nicholas Piggin
2025-03-11 12:57 ` [PULL 25/72] ppc/xive2: Add grouping level to notification Nicholas Piggin
2025-03-11 12:57 ` [PULL 26/72] ppc/xive2: Support group-matching when looking for target Nicholas Piggin
2025-03-11 12:57 ` [PULL 27/72] ppc/xive2: Add undelivered group interrupt to backlog Nicholas Piggin
2025-03-11 12:57 ` [PULL 28/72] ppc/xive2: Process group backlog when pushing an OS context Nicholas Piggin
2025-03-11 12:57 ` [PULL 29/72] ppc/xive2: Process group backlog when updating the CPPR Nicholas Piggin
2025-03-11 12:57 ` [PULL 30/72] qtest/xive: Add group-interrupt test Nicholas Piggin
2025-03-11 12:57 ` [PULL 31/72] ppc/xive2: Add support for MMIO operations on the NVPG/NVC BAR Nicholas Piggin
2025-03-11 12:57 ` [PULL 32/72] ppc/xive2: Support crowd-matching when looking for target Nicholas Piggin
2025-03-11 12:57 ` [PULL 33/72] pnv/xive2: Rename nvp_ to nvx_ if they can refer to NVP or NVGC Nicholas Piggin
2025-03-11 12:57 ` [PULL 34/72] ppc/xive2: Check crowd backlog when scanning group backlog Nicholas Piggin
2025-03-11 12:57 ` [PULL 35/72] qtest/xive: Change printf to g_test_message Nicholas Piggin
2025-03-11 12:57 ` [PULL 36/72] qtest/xive: Add test of pool interrupts Nicholas Piggin
2025-03-11 12:57 ` [PULL 37/72] hw/ssi/pnv_spi: Replace PnvXferBuffer with Fifo8 structure Nicholas Piggin
2025-03-11 12:57 ` Nicholas Piggin [this message]
2025-03-11 12:57 ` [PULL 39/72] hw/ssi/pnv_spi: Make bus names distinct for each controllers of a socket Nicholas Piggin
2025-03-11 12:57 ` [PULL 40/72] hw/ssi/pnv_spi: Put a limit to RDR match failures Nicholas Piggin
2025-03-11 12:57 ` [PULL 41/72] hw/ppc/spapr: Restrict CONFER hypercall to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 42/72] ppc/pnv: Add new PowerPC Special Purpose Registers (RWMR) Nicholas Piggin
2025-03-11 12:57 ` [PULL 43/72] target/ppc: Make ppc_ldl_code() declaration public Nicholas Piggin
2025-03-11 12:57 ` [PULL 44/72] target/ppc: Move TCG specific exception handlers to tcg-excp_helper.c Nicholas Piggin
2025-03-11 12:57 ` [PULL 45/72] target/ppc: Move ppc_ldl_code() " Nicholas Piggin
2025-03-11 12:57 ` [PULL 46/72] target/ppc: Ensure powerpc_mcheck_checkstop() is only called under TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 47/72] target/ppc: Restrict powerpc_checkstop() to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 48/72] target/ppc: Remove raise_exception_ra() Nicholas Piggin
2025-03-11 12:57 ` [PULL 49/72] target/ppc: Restrict exception helpers to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 50/72] target/ppc: Restrict various common " Nicholas Piggin
2025-03-11 12:57 ` [PULL 51/72] target/ppc: Fix style in excp_helper.c Nicholas Piggin
2025-03-11 12:57 ` [PULL 52/72] target/ppc: Make powerpc_excp() prototype public Nicholas Piggin
2025-03-11 12:57 ` [PULL 53/72] target/ppc: Restrict ATTN / SCV / PMINSN helpers to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 54/72] hw/ppc/spapr: Convert HPTE() macro as hpte_get_ptr() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 55/72] hw/ppc/spapr: Convert HPTE_VALID() macro as hpte_is_valid() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 56/72] hw/ppc/spapr: Convert HPTE_DIRTY() macro as hpte_is_dirty() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 57/72] hw/ppc/spapr: Convert CLEAN_HPTE() macro as hpte_set_clean() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 58/72] hw/ppc/spapr: Convert DIRTY_HPTE() macro as hpte_set_dirty() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 59/72] hw/ppc/epapr: Do not swap ePAPR magic value Nicholas Piggin
2025-03-11 12:57 ` [PULL 60/72] ppc: Enable 2nd DAWR support on Power10 PowerNV machine Nicholas Piggin
2025-03-11 12:57 ` [PULL 61/72] ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine Nicholas Piggin
2025-03-11 12:57 ` [PULL 62/72] spapr: nested: Add support for reporting Hostwide state counter Nicholas Piggin
2025-03-11 12:57 ` [PULL 63/72] target/ppc: fix timebase register reset state Nicholas Piggin
2025-03-11 12:57 ` [PULL 64/72] target/ppc: Wire up BookE ATB registers for e500 family Nicholas Piggin
2025-03-11 12:57 ` [PULL 65/72] target/ppc: Avoid warning message for zero process table entries Nicholas Piggin
2025-03-11 12:58 ` [PULL 66/72] spapr: Generate random HASHPKEYR for spapr machines Nicholas Piggin
2025-03-11 12:58 ` [PULL 67/72] ppc/amigaone: Simplify replacement dummy_fw Nicholas Piggin
2025-03-11 12:58 ` [PULL 68/72] ppc/amigaone: Implement NVRAM emulation Nicholas Piggin
2025-03-11 12:58 ` [PULL 69/72] ppc/amigaone: Add default environment Nicholas Piggin
2025-03-11 12:58 ` [PULL 70/72] ppc/amigaone: Add kernel and initrd support Nicholas Piggin
2025-06-16 10:07 ` Philippe Mathieu-Daudé
2025-06-16 10:38 ` BALATON Zoltan
2025-10-21 15:36 ` Peter Maydell
2025-03-11 12:58 ` [PULL 71/72] ppc/amigaone: Add #defines for memory map constants Nicholas Piggin
2025-03-11 12:58 ` [PULL 72/72] docs/system/ppc/amigang.rst: Update for NVRAM emulation Nicholas Piggin
2025-03-13 2:34 ` [PULL 00/72] ppc-for-10.0-1 queue Stefan Hajnoczi
2025-03-13 6:13 ` Thomas Huth
2025-03-13 10:49 ` Philippe Mathieu-Daudé
2025-03-14 2:34 ` Nicholas Piggin
2025-03-14 6:19 ` Thomas Huth
2025-03-14 2:41 ` Nicholas Piggin
2025-03-13 7:05 ` Stefan Hajnoczi
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