Re: [PATCH 4/4] PCI: j721e: Add support to build as a loadable module

[Siddharth Vadapalli <s-vadapalli@ti.com>]

On Fri, Mar 14, 2025 at 10:03:01AM +0100, Thomas Richard wrote:

Hello Thomas,

> > +
> > +	if (pcie->reset_gpio) {
> > +		msleep(PCIE_T_PVPERL_MS);
> > +		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> > +	}
> > +
> > +	if (pcie->refclk)
> > +		clk_disable_unprepare(pcie->refclk);
> >  
> 
> Hello Siddharth,
> 
> I think clk_disable_unprepare() is a no-op if the clock is NULL, so the
> if statement is useless.
> 
> https://elixir.bootlin.com/linux/v6.14-rc6/source/include/linux/clk.h#L1157
> https://elixir.bootlin.com/linux/v6.14-rc6/source/drivers/clk/clk.c#L1237
> https://elixir.bootlin.com/linux/v6.14-rc6/source/drivers/clk/clk.c#L1099

Thank you for pointing it out. I will drop the unnecessary check in the
next version. I will wait for feedback on other patches in this series
before I post the next version.

Regards,
Siddharth.