* Re: [PATCH v2 6/6] clk: clk-axi-clkgen: fix coding style issues
@ 2025-03-16 16:19 kernel test robot
0 siblings, 0 replies; 6+ messages in thread
From: kernel test robot @ 2025-03-16 16:19 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp, Dan Carpenter
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250313-dev-axi-clkgen-limits-v2-6-173ae2ad6311@analog.com>
References: <20250313-dev-axi-clkgen-limits-v2-6-173ae2ad6311@analog.com>
TO: "Nuno Sá via B4 Relay" <devnull+nuno.sa.analog.com@kernel.org>
TO: linux-clk@vger.kernel.org
TO: linux-fpga@vger.kernel.org
CC: Stephen Boyd <sboyd@kernel.org>
CC: Michael Turquette <mturquette@baylibre.com>
CC: Moritz Fischer <mdf@kernel.org>
CC: Wu Hao <hao.wu@intel.com>
CC: Xu Yilun <yilun.xu@intel.com>
CC: Tom Rix <trix@redhat.com>
Hi Nuno,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 82f69876ef45ad66c0b114b786c7c6ac0f6a4580]
url: https://github.com/intel-lab-lkp/linux/commits/Nuno-S-via-B4-Relay/clk-clk-axi-clkgen-fix-fpfd_max-frequency-for-zynq/20250313-231624
base: 82f69876ef45ad66c0b114b786c7c6ac0f6a4580
patch link: https://lore.kernel.org/r/20250313-dev-axi-clkgen-limits-v2-6-173ae2ad6311%40analog.com
patch subject: [PATCH v2 6/6] clk: clk-axi-clkgen: fix coding style issues
:::::: branch date: 3 days ago
:::::: commit date: 3 days ago
config: riscv-randconfig-r073-20250316 (https://download.01.org/0day-ci/archive/20250316/202503162319.83BPHA2N-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 14.2.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202503162319.83BPHA2N-lkp@intel.com/
smatch warnings:
drivers/clk/clk-axi-clkgen.c:229 axi_clkgen_calc_clk_params() warn: add some parenthesis here?
vim +229 drivers/clk/clk-axi-clkgen.c
86378cf646d323d Lars-Peter Clausen 2020-10-01 198
86378cf646d323d Lars-Peter Clausen 2020-10-01 199 static void axi_clkgen_calc_clk_params(unsigned int divider,
d737515c8ea3e30 Nuno Sá 2025-03-13 200 unsigned int frac_divider,
d737515c8ea3e30 Nuno Sá 2025-03-13 201 struct axi_clkgen_div_params *params)
0e646c52cf0ee18 Lars-Peter Clausen 2013-03-11 202 {
86378cf646d323d Lars-Peter Clausen 2020-10-01 203 memset(params, 0x0, sizeof(*params));
86378cf646d323d Lars-Peter Clausen 2020-10-01 204
86378cf646d323d Lars-Peter Clausen 2020-10-01 205 if (divider == 1) {
86378cf646d323d Lars-Peter Clausen 2020-10-01 206 params->nocount = 1;
86378cf646d323d Lars-Peter Clausen 2020-10-01 207 return;
86378cf646d323d Lars-Peter Clausen 2020-10-01 208 }
86378cf646d323d Lars-Peter Clausen 2020-10-01 209
86378cf646d323d Lars-Peter Clausen 2020-10-01 210 if (frac_divider == 0) {
86378cf646d323d Lars-Peter Clausen 2020-10-01 211 params->high = divider / 2;
86378cf646d323d Lars-Peter Clausen 2020-10-01 212 params->edge = divider % 2;
86378cf646d323d Lars-Peter Clausen 2020-10-01 213 params->low = divider - params->high;
86378cf646d323d Lars-Peter Clausen 2020-10-01 214 } else {
86378cf646d323d Lars-Peter Clausen 2020-10-01 215 params->frac_en = 1;
86378cf646d323d Lars-Peter Clausen 2020-10-01 216 params->frac = frac_divider;
86378cf646d323d Lars-Peter Clausen 2020-10-01 217
86378cf646d323d Lars-Peter Clausen 2020-10-01 218 params->high = divider / 2;
86378cf646d323d Lars-Peter Clausen 2020-10-01 219 params->edge = divider % 2;
86378cf646d323d Lars-Peter Clausen 2020-10-01 220 params->low = params->high;
86378cf646d323d Lars-Peter Clausen 2020-10-01 221
86378cf646d323d Lars-Peter Clausen 2020-10-01 222 if (params->edge == 0) {
86378cf646d323d Lars-Peter Clausen 2020-10-01 223 params->high--;
86378cf646d323d Lars-Peter Clausen 2020-10-01 224 params->frac_wf_r = 1;
86378cf646d323d Lars-Peter Clausen 2020-10-01 225 }
86378cf646d323d Lars-Peter Clausen 2020-10-01 226
86378cf646d323d Lars-Peter Clausen 2020-10-01 227 if (params->edge == 0 || frac_divider == 1)
86378cf646d323d Lars-Peter Clausen 2020-10-01 228 params->low--;
d737515c8ea3e30 Nuno Sá 2025-03-13 @229 if ((params->edge == 0 ^ frac_divider == 1) ||
86378cf646d323d Lars-Peter Clausen 2020-10-01 230 (divider == 2 && frac_divider == 1))
86378cf646d323d Lars-Peter Clausen 2020-10-01 231 params->frac_wf_f = 1;
86378cf646d323d Lars-Peter Clausen 2020-10-01 232
86378cf646d323d Lars-Peter Clausen 2020-10-01 233 params->frac_phase = params->edge * 4 + frac_divider / 2;
86378cf646d323d Lars-Peter Clausen 2020-10-01 234 }
0e646c52cf0ee18 Lars-Peter Clausen 2013-03-11 235 }
0e646c52cf0ee18 Lars-Peter Clausen 2013-03-11 236
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 0/6] clk: clk-axi-clkgen: improvements and some fixes
@ 2025-03-13 15:14 Nuno Sá
2025-03-13 15:14 ` Nuno Sá via B4 Relay
0 siblings, 1 reply; 6+ messages in thread
From: Nuno Sá @ 2025-03-13 15:14 UTC (permalink / raw)
To: linux-clk, linux-fpga
Cc: Stephen Boyd, Michael Turquette, Moritz Fischer, Wu Hao, Xu Yilun,
Tom Rix
This series starts with a small fix and then a bunch of small
improvements. The main change though is to allow detecting of
struct axi_clkgen_limits during probe().
---
Changes in v2:
- Patch 3
* Rename adi_axi_fgpa_technology -> adi_axi_fpga_technology.
- Link to v1: https://lore.kernel.org/r/20250219-dev-axi-clkgen-limits-v1-0-26f7ef14cd9c@analog.com
---
Nuno Sá (6):
clk: clk-axi-clkgen: fix fpfd_max frequency for zynq
clk: clk-axi-clkgen: make sure to include mod_devicetable.h
include: fpga: adi-axi-common: add new helper macros
clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime
clk: clk-axi-clkgen move to min/max()
clk: clk-axi-clkgen: fix coding style issues
drivers/clk/clk-axi-clkgen.c | 149 +++++++++++++++++++++++++-----------
include/linux/fpga/adi-axi-common.h | 35 +++++++++
2 files changed, 141 insertions(+), 43 deletions(-)
---
base-commit: 82f69876ef45ad66c0b114b786c7c6ac0f6a4580
change-id: 20250218-dev-axi-clkgen-limits-63fb0c5ec38b
--
Thanks!
- Nuno Sá
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 6/6] clk: clk-axi-clkgen: fix coding style issues 2025-03-13 15:14 [PATCH v2 0/6] clk: clk-axi-clkgen: improvements and some fixes Nuno Sá @ 2025-03-13 15:14 ` Nuno Sá via B4 Relay 0 siblings, 0 replies; 6+ messages in thread From: Nuno Sá @ 2025-03-13 15:14 UTC (permalink / raw) To: linux-clk, linux-fpga Cc: Stephen Boyd, Michael Turquette, Moritz Fischer, Wu Hao, Xu Yilun, Tom Rix This is just cosmetics and so no functional changes intended. Signed-off-by: Nuno Sá <nuno.sa@analog.com> --- drivers/clk/clk-axi-clkgen.c | 76 +++++++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 82a99c3b9063cd2dd8a9dc7fdec81a38feee12b9..c2b5c01698455075ad01d5fad356aa162c53b3bc 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -15,6 +15,7 @@ #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/err.h> +#include <linux/types.h> #include <linux/fpga/adi-axi-common.h> @@ -93,7 +94,7 @@ static uint32_t axi_clkgen_lookup_filter(unsigned int m) } } -static const uint32_t axi_clkgen_lock_table[] = { +static const u32 axi_clkgen_lock_table[] = { 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8, 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8, 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339, @@ -105,7 +106,7 @@ static const uint32_t axi_clkgen_lock_table[] = { 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113, }; -static uint32_t axi_clkgen_lookup_lock(unsigned int m) +static u32 axi_clkgen_lookup_lock(unsigned int m) { if (m < ARRAY_SIZE(axi_clkgen_lock_table)) return axi_clkgen_lock_table[m]; @@ -127,8 +128,9 @@ static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { }; static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, - unsigned long fin, unsigned long fout, - unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout) + unsigned long fin, unsigned long fout, + unsigned int *best_d, unsigned int *best_m, + unsigned int *best_dout) { unsigned long d, d_min, d_max, _d_min, _d_max; unsigned long m, m_min, m_max; @@ -195,9 +197,9 @@ struct axi_clkgen_div_params { }; static void axi_clkgen_calc_clk_params(unsigned int divider, - unsigned int frac_divider, struct axi_clkgen_div_params *params) + unsigned int frac_divider, + struct axi_clkgen_div_params *params) { - memset(params, 0x0, sizeof(*params)); if (divider == 1) { @@ -224,8 +226,8 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, if (params->edge == 0 || frac_divider == 1) params->low--; - if (((params->edge == 0) ^ (frac_divider == 1)) || - (divider == 2 && frac_divider == 1)) + if ((params->edge == 0 ^ frac_divider == 1) || + (divider == 2 && frac_divider == 1)) params->frac_wf_f = 1; params->frac_phase = params->edge * 4 + frac_divider / 2; @@ -233,13 +235,13 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, } static void axi_clkgen_write(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int val) + unsigned int reg, unsigned int val) { writel(val, axi_clkgen->base + reg); } static void axi_clkgen_read(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int *val) + unsigned int reg, unsigned int *val) { *val = readl(axi_clkgen->base + reg); } @@ -260,7 +262,7 @@ static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen) } static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int *val) + unsigned int reg, unsigned int *val) { unsigned int reg_val; int ret; @@ -284,7 +286,8 @@ static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, } static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int val, unsigned int mask) + unsigned int reg, unsigned int val, + unsigned int mask) { unsigned int reg_val = 0; int ret; @@ -305,8 +308,7 @@ static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, return 0; } -static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, - bool enable) +static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, bool enable) { unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE; @@ -322,31 +324,31 @@ static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw) } static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen, - unsigned int reg1, unsigned int reg2, unsigned int reg3, - struct axi_clkgen_div_params *params) + unsigned int reg1, unsigned int reg2, + unsigned int reg3, + struct axi_clkgen_div_params *params) { axi_clkgen_mmcm_write(axi_clkgen, reg1, - (params->high << 6) | params->low, 0xefff); + (params->high << 6) | params->low, 0xefff); axi_clkgen_mmcm_write(axi_clkgen, reg2, - (params->frac << 12) | (params->frac_en << 11) | - (params->frac_wf_r << 10) | (params->edge << 7) | - (params->nocount << 6), 0x7fff); + (params->frac << 12) | (params->frac_en << 11) | + (params->frac_wf_r << 10) | (params->edge << 7) | + (params->nocount << 6), 0x7fff); if (reg3 != 0) { axi_clkgen_mmcm_write(axi_clkgen, reg3, - (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00); + (params->frac_phase << 11) | (params->frac_wf_f << 10), + 0x3c00); } } -static int axi_clkgen_set_rate(struct clk_hw *clk_hw, - unsigned long rate, unsigned long parent_rate) +static int axi_clkgen_set_rate(struct clk_hw *clk_hw, unsigned long rate, + unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); const struct axi_clkgen_limits *limits = &axi_clkgen->limits; unsigned int d, m, dout; struct axi_clkgen_div_params params; - uint32_t power = 0; - uint32_t filter; - uint32_t lock; + u32 power = 0, filter, lock; if (parent_rate == 0 || rate == 0) return -EINVAL; @@ -366,22 +368,22 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, ¶ms); axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2, - MMCM_REG_CLKOUT5_2, ¶ms); + MMCM_REG_CLKOUT5_2, ¶ms); axi_clkgen_calc_clk_params(d, 0, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV, - (params.edge << 13) | (params.nocount << 12) | - (params.high << 6) | params.low, 0x3fff); + (params.edge << 13) | (params.nocount << 12) | + (params.high << 6) | params.low, 0x3fff); axi_clkgen_calc_clk_params(m >> 3, m & 0x7, ¶ms); axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2, - MMCM_REG_CLKOUT6_2, ¶ms); + MMCM_REG_CLKOUT6_2, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2, - (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); + (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3, - (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); + (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900); @@ -410,7 +412,7 @@ static int axi_clkgen_determine_rate(struct clk_hw *hw, } static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, - unsigned int reg1, unsigned int reg2) + unsigned int reg1, unsigned int reg2) { unsigned int val1, val2; unsigned int div; @@ -437,7 +439,7 @@ static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, } static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, - unsigned long parent_rate) + unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); unsigned int d, m, dout; @@ -445,9 +447,9 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, unsigned int val; dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1, - MMCM_REG_CLKOUT0_2); + MMCM_REG_CLKOUT0_2); m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1, - MMCM_REG_CLK_FB2); + MMCM_REG_CLK_FB2); axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val); if (val & MMCM_CLK_DIV_NOCOUNT) @@ -620,7 +622,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names", - &clk_name); + &clk_name); init.name = clk_name; init.ops = &axi_clkgen_ops; -- 2.48.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 6/6] clk: clk-axi-clkgen: fix coding style issues @ 2025-03-13 15:14 ` Nuno Sá via B4 Relay 0 siblings, 0 replies; 6+ messages in thread From: Nuno Sá via B4 Relay @ 2025-03-13 15:14 UTC (permalink / raw) To: linux-clk, linux-fpga Cc: Stephen Boyd, Michael Turquette, Moritz Fischer, Wu Hao, Xu Yilun, Tom Rix From: Nuno Sá <nuno.sa@analog.com> This is just cosmetics and so no functional changes intended. Signed-off-by: Nuno Sá <nuno.sa@analog.com> --- drivers/clk/clk-axi-clkgen.c | 76 +++++++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 82a99c3b9063cd2dd8a9dc7fdec81a38feee12b9..c2b5c01698455075ad01d5fad356aa162c53b3bc 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -15,6 +15,7 @@ #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/err.h> +#include <linux/types.h> #include <linux/fpga/adi-axi-common.h> @@ -93,7 +94,7 @@ static uint32_t axi_clkgen_lookup_filter(unsigned int m) } } -static const uint32_t axi_clkgen_lock_table[] = { +static const u32 axi_clkgen_lock_table[] = { 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8, 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8, 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339, @@ -105,7 +106,7 @@ static const uint32_t axi_clkgen_lock_table[] = { 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113, }; -static uint32_t axi_clkgen_lookup_lock(unsigned int m) +static u32 axi_clkgen_lookup_lock(unsigned int m) { if (m < ARRAY_SIZE(axi_clkgen_lock_table)) return axi_clkgen_lock_table[m]; @@ -127,8 +128,9 @@ static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { }; static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, - unsigned long fin, unsigned long fout, - unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout) + unsigned long fin, unsigned long fout, + unsigned int *best_d, unsigned int *best_m, + unsigned int *best_dout) { unsigned long d, d_min, d_max, _d_min, _d_max; unsigned long m, m_min, m_max; @@ -195,9 +197,9 @@ struct axi_clkgen_div_params { }; static void axi_clkgen_calc_clk_params(unsigned int divider, - unsigned int frac_divider, struct axi_clkgen_div_params *params) + unsigned int frac_divider, + struct axi_clkgen_div_params *params) { - memset(params, 0x0, sizeof(*params)); if (divider == 1) { @@ -224,8 +226,8 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, if (params->edge == 0 || frac_divider == 1) params->low--; - if (((params->edge == 0) ^ (frac_divider == 1)) || - (divider == 2 && frac_divider == 1)) + if ((params->edge == 0 ^ frac_divider == 1) || + (divider == 2 && frac_divider == 1)) params->frac_wf_f = 1; params->frac_phase = params->edge * 4 + frac_divider / 2; @@ -233,13 +235,13 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, } static void axi_clkgen_write(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int val) + unsigned int reg, unsigned int val) { writel(val, axi_clkgen->base + reg); } static void axi_clkgen_read(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int *val) + unsigned int reg, unsigned int *val) { *val = readl(axi_clkgen->base + reg); } @@ -260,7 +262,7 @@ static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen) } static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int *val) + unsigned int reg, unsigned int *val) { unsigned int reg_val; int ret; @@ -284,7 +286,8 @@ static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, } static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, - unsigned int reg, unsigned int val, unsigned int mask) + unsigned int reg, unsigned int val, + unsigned int mask) { unsigned int reg_val = 0; int ret; @@ -305,8 +308,7 @@ static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, return 0; } -static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, - bool enable) +static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, bool enable) { unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE; @@ -322,31 +324,31 @@ static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw) } static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen, - unsigned int reg1, unsigned int reg2, unsigned int reg3, - struct axi_clkgen_div_params *params) + unsigned int reg1, unsigned int reg2, + unsigned int reg3, + struct axi_clkgen_div_params *params) { axi_clkgen_mmcm_write(axi_clkgen, reg1, - (params->high << 6) | params->low, 0xefff); + (params->high << 6) | params->low, 0xefff); axi_clkgen_mmcm_write(axi_clkgen, reg2, - (params->frac << 12) | (params->frac_en << 11) | - (params->frac_wf_r << 10) | (params->edge << 7) | - (params->nocount << 6), 0x7fff); + (params->frac << 12) | (params->frac_en << 11) | + (params->frac_wf_r << 10) | (params->edge << 7) | + (params->nocount << 6), 0x7fff); if (reg3 != 0) { axi_clkgen_mmcm_write(axi_clkgen, reg3, - (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00); + (params->frac_phase << 11) | (params->frac_wf_f << 10), + 0x3c00); } } -static int axi_clkgen_set_rate(struct clk_hw *clk_hw, - unsigned long rate, unsigned long parent_rate) +static int axi_clkgen_set_rate(struct clk_hw *clk_hw, unsigned long rate, + unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); const struct axi_clkgen_limits *limits = &axi_clkgen->limits; unsigned int d, m, dout; struct axi_clkgen_div_params params; - uint32_t power = 0; - uint32_t filter; - uint32_t lock; + u32 power = 0, filter, lock; if (parent_rate == 0 || rate == 0) return -EINVAL; @@ -366,22 +368,22 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, ¶ms); axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2, - MMCM_REG_CLKOUT5_2, ¶ms); + MMCM_REG_CLKOUT5_2, ¶ms); axi_clkgen_calc_clk_params(d, 0, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV, - (params.edge << 13) | (params.nocount << 12) | - (params.high << 6) | params.low, 0x3fff); + (params.edge << 13) | (params.nocount << 12) | + (params.high << 6) | params.low, 0x3fff); axi_clkgen_calc_clk_params(m >> 3, m & 0x7, ¶ms); axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2, - MMCM_REG_CLKOUT6_2, ¶ms); + MMCM_REG_CLKOUT6_2, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2, - (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); + (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3, - (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); + (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900); @@ -410,7 +412,7 @@ static int axi_clkgen_determine_rate(struct clk_hw *hw, } static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, - unsigned int reg1, unsigned int reg2) + unsigned int reg1, unsigned int reg2) { unsigned int val1, val2; unsigned int div; @@ -437,7 +439,7 @@ static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, } static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, - unsigned long parent_rate) + unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); unsigned int d, m, dout; @@ -445,9 +447,9 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, unsigned int val; dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1, - MMCM_REG_CLKOUT0_2); + MMCM_REG_CLKOUT0_2); m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1, - MMCM_REG_CLK_FB2); + MMCM_REG_CLK_FB2); axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val); if (val & MMCM_CLK_DIV_NOCOUNT) @@ -620,7 +622,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names", - &clk_name); + &clk_name); init.name = clk_name; init.ops = &axi_clkgen_ops; -- 2.48.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 6/6] clk: clk-axi-clkgen: fix coding style issues 2025-03-13 15:14 ` Nuno Sá via B4 Relay (?) @ 2025-03-14 9:23 ` kernel test robot -1 siblings, 0 replies; 6+ messages in thread From: kernel test robot @ 2025-03-14 9:23 UTC (permalink / raw) To: Nuno Sá via B4 Relay, linux-clk, linux-fpga Cc: oe-kbuild-all, Stephen Boyd, Michael Turquette, Moritz Fischer, Wu Hao, Xu Yilun, Tom Rix Hi Nuno, kernel test robot noticed the following build warnings: [auto build test WARNING on 82f69876ef45ad66c0b114b786c7c6ac0f6a4580] url: https://github.com/intel-lab-lkp/linux/commits/Nuno-S-via-B4-Relay/clk-clk-axi-clkgen-fix-fpfd_max-frequency-for-zynq/20250313-231624 base: 82f69876ef45ad66c0b114b786c7c6ac0f6a4580 patch link: https://lore.kernel.org/r/20250313-dev-axi-clkgen-limits-v2-6-173ae2ad6311%40analog.com patch subject: [PATCH v2 6/6] clk: clk-axi-clkgen: fix coding style issues config: riscv-randconfig-002-20250314 (https://download.01.org/0day-ci/archive/20250314/202503141741.UAwRQuuG-lkp@intel.com/config) compiler: riscv64-linux-gcc (GCC) 14.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250314/202503141741.UAwRQuuG-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202503141741.UAwRQuuG-lkp@intel.com/ All warnings (new ones prefixed by >>): drivers/clk/clk-axi-clkgen.c: In function 'axi_clkgen_calc_clk_params': >> drivers/clk/clk-axi-clkgen.c:229:35: warning: suggest parentheses around comparison in operand of '^' [-Wparentheses] 229 | if ((params->edge == 0 ^ frac_divider == 1) || | ~~~~~~~~~~~~~^~~~ vim +229 drivers/clk/clk-axi-clkgen.c 198 199 static void axi_clkgen_calc_clk_params(unsigned int divider, 200 unsigned int frac_divider, 201 struct axi_clkgen_div_params *params) 202 { 203 memset(params, 0x0, sizeof(*params)); 204 205 if (divider == 1) { 206 params->nocount = 1; 207 return; 208 } 209 210 if (frac_divider == 0) { 211 params->high = divider / 2; 212 params->edge = divider % 2; 213 params->low = divider - params->high; 214 } else { 215 params->frac_en = 1; 216 params->frac = frac_divider; 217 218 params->high = divider / 2; 219 params->edge = divider % 2; 220 params->low = params->high; 221 222 if (params->edge == 0) { 223 params->high--; 224 params->frac_wf_r = 1; 225 } 226 227 if (params->edge == 0 || frac_divider == 1) 228 params->low--; > 229 if ((params->edge == 0 ^ frac_divider == 1) || 230 (divider == 2 && frac_divider == 1)) 231 params->frac_wf_f = 1; 232 233 params->frac_phase = params->edge * 4 + frac_divider / 2; 234 } 235 } 236 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 6/6] clk: clk-axi-clkgen: fix coding style issues 2025-03-13 15:14 ` Nuno Sá via B4 Relay (?) (?) @ 2025-03-17 5:26 ` Dan Carpenter 2025-03-17 16:47 ` Nuno Sá -1 siblings, 1 reply; 6+ messages in thread From: Dan Carpenter @ 2025-03-17 5:26 UTC (permalink / raw) To: Nuno Sá Cc: linux-clk, linux-fpga, Stephen Boyd, Michael Turquette, Moritz Fischer, Wu Hao, Xu Yilun, Tom Rix On Thu, Mar 13, 2025 at 03:14:48PM +0000, Nuno Sá wrote: > @@ -224,8 +226,8 @@ static void axi_clkgen_calc_clk_params(unsigned int divider, > > if (params->edge == 0 || frac_divider == 1) > params->low--; > - if (((params->edge == 0) ^ (frac_divider == 1)) || ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > - (divider == 2 && frac_divider == 1)) > + if ((params->edge == 0 ^ frac_divider == 1) || ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This works, but the code was a lot easier to read with parentheses. regards, dan carpenter ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 6/6] clk: clk-axi-clkgen: fix coding style issues 2025-03-17 5:26 ` Dan Carpenter @ 2025-03-17 16:47 ` Nuno Sá 0 siblings, 0 replies; 6+ messages in thread From: Nuno Sá @ 2025-03-17 16:47 UTC (permalink / raw) To: Dan Carpenter, Nuno Sá Cc: linux-clk, linux-fpga, Stephen Boyd, Michael Turquette, Moritz Fischer, Wu Hao, Xu Yilun, Tom Rix On Mon, 2025-03-17 at 08:26 +0300, Dan Carpenter wrote: > On Thu, Mar 13, 2025 at 03:14:48PM +0000, Nuno Sá wrote: > > @@ -224,8 +226,8 @@ static void axi_clkgen_calc_clk_params(unsigned int > > divider, > > > > if (params->edge == 0 || frac_divider == 1) > > params->low--; > > - if (((params->edge == 0) ^ (frac_divider == 1)) || > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > > > - (divider == 2 && frac_divider == 1)) > > + if ((params->edge == 0 ^ frac_divider == 1) || > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > This works, but the code was a lot easier to read with parentheses. > > Yes, I'll do it in v3. Just waiting a few more days for additional comments. - Nuno Sá ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-03-17 16:47 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-03-16 16:19 [PATCH v2 6/6] clk: clk-axi-clkgen: fix coding style issues kernel test robot -- strict thread matches above, loose matches on Subject: below -- 2025-03-13 15:14 [PATCH v2 0/6] clk: clk-axi-clkgen: improvements and some fixes Nuno Sá 2025-03-13 15:14 ` [PATCH v2 6/6] clk: clk-axi-clkgen: fix coding style issues Nuno Sá 2025-03-13 15:14 ` Nuno Sá via B4 Relay 2025-03-14 9:23 ` kernel test robot 2025-03-17 5:26 ` Dan Carpenter 2025-03-17 16:47 ` Nuno Sá
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