From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <alejandro.lucero-palau@amd.com>
Cc: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
<dan.j.williams@intel.com>, <edward.cree@amd.com>,
<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
<edumazet@google.com>, <dave.jiang@intel.com>,
Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v12 04/23] cxl: move register/capability check to driver
Date: Fri, 4 Apr 2025 16:47:44 +0100 [thread overview]
Message-ID: <20250404164744.00004b34@huawei.com> (raw)
In-Reply-To: <20250331144555.1947819-5-alejandro.lucero-palau@amd.com>
On Mon, 31 Mar 2025 15:45:36 +0100
<alejandro.lucero-palau@amd.com> wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Type3 has some mandatory capabilities which are optional for Type2.
>
> In order to support same register/capability discovery code for both
> types, avoid any assumption about what capabilities should be there, and
> export the capabilities found for the caller doing the capabilities
> check based on the expected ones.
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
A few minor things inline.
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 0fd6646c1a2e..7adf2cff43b6 100644
> @@ -37,7 +39,8 @@
> * Probe for component register information and return it in map object.
> */
> void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> - struct cxl_component_reg_map *map)
> + struct cxl_component_reg_map *map,
> + unsigned long *caps)
> {
> int cap, cap_count;
> u32 cap_array;
> @@ -85,6 +88,8 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> decoder_cnt = cxl_hdm_decoder_count(hdr);
> length = 0x20 * decoder_cnt + 0x10;
> rmap = &map->hdm_decoder;
> + if (caps)
> + set_bit(CXL_DEV_CAP_HDM, caps);
Maybe it's worth a local helper?
cxl_set_cap_bit() that checks for NULL cap
#define cxl_set_cap_bit(bit, caps) if (caps) { set_bit((bit), (caps)); }
Or just always provide caps. Do we have use cases where we really don't
care about what is found?
> break;
> }
> case CXL_CM_CAP_CAP_ID_RAS:
> @@ -92,6 +97,8 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> offset);
> length = CXL_RAS_CAPABILITY_LENGTH;
> rmap = &map->ras;
> + if (caps)
> + set_bit(CXL_DEV_CAP_RAS, caps);
> break;
> default:
> dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id,
> #endif /* __CXL_PCI_H__ */
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index e8c0efb3a12f..2a52556bd568 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -836,6 +836,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> else if (!cxlds->reg_map.component_map.ras.valid)
> @@ -895,6 +909,17 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> if (rc)
> dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
>
> + /*
> + * Checking mandatory caps are there as, at least, a subset of those
> + * found.
> + */
> + if (!bitmap_subset(expected, found, CXL_MAX_CAPS)) {
> + dev_err(&pdev->dev,
> + "Found capabilities (%pb) not containing mandatory expected: (%pb)\n",
The only obvious reason I can see for an expected bitmap is this print and this isn't
that helpful as requires anyone seeing it to dig into what the bitmap means. Maybe
if (!test_bit(CXL_DEV_CAP_HDM, found))
return dev_err_probe(&pdev->dev, -ENXIO "HDM decoder capability not found\n");
etc.
That will only print the first once not found though and avoiding that adds complexity we
probably don't want here.
> + found, expected);
> + return -ENXIO;
> + }
> +
> rc = cxl_pci_type3_init_mailbox(cxlds);
> if (rc)
> return rc;
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 1383fd724cf6..b9cd98950a38 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -25,6 +25,26 @@ enum cxl_devtype {
>
> struct device;
>
> +
> +/* Capabilities as defined for:
CXL code so
/*
* Capabilities...
> + *
> + * Component Registers (Table 8-22 CXL 3.2 specification)
> + * Device Registers (8.2.8.2.1 CXL 3.2 specification)
> + *
> + * and currently being used for kernel CXL support.
> + */
> +
> +enum cxl_dev_cap {
> + /* capabilities from Component Registers */
> + CXL_DEV_CAP_RAS,
> + CXL_DEV_CAP_HDM,
> + /* capabilities from Device Registers */
> + CXL_DEV_CAP_DEV_STATUS,
> + CXL_DEV_CAP_MAILBOX_PRIMARY,
> + CXL_DEV_CAP_MEMDEV,
> + CXL_MAX_CAPS,
No comma as this is at terminating entry. Seems unlikely to make
sense to ever have anything after it so let us make that harder /
more obvious in future patches, but not having the comma.
> +};
> +
> /*
> * Using struct_group() allows for per register-block-type helper routines,
> * without requiring block-type agnostic code to include the prefix.
next prev parent reply other threads:[~2025-04-04 15:47 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-31 14:45 [PATCH v12 00/23] cxl: add type2 device basic support alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 01/23] " alejandro.lucero-palau
2025-04-01 17:36 ` Alejandro Lucero Palau
2025-04-04 15:24 ` Jonathan Cameron
2025-04-07 9:50 ` Alejandro Lucero Palau
2025-04-10 8:12 ` Alejandro Lucero Palau
2025-04-07 16:55 ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 02/23] sfc: add cxl support alejandro.lucero-palau
2025-03-31 18:31 ` Simon Horman
2025-04-07 13:59 ` Alejandro Lucero Palau
2025-04-04 15:29 ` Jonathan Cameron
2025-03-31 14:45 ` [PATCH v12 03/23] cxl: move pci generic code alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 04/23] cxl: move register/capability check to driver alejandro.lucero-palau
2025-04-04 15:47 ` Jonathan Cameron [this message]
2025-04-07 13:40 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 05/23] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-03-31 18:33 ` Simon Horman
2025-04-07 14:00 ` Alejandro Lucero Palau
2025-04-04 16:03 ` Jonathan Cameron
2025-04-07 10:04 ` Alejandro Lucero Palau
2025-04-15 16:34 ` Jonathan Cameron
2025-03-31 14:45 ` [PATCH v12 06/23] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 07/23] cxl: support dpa initialization without a mailbox alejandro.lucero-palau
2025-04-04 16:05 ` Jonathan Cameron
2025-04-07 10:53 ` Alejandro Lucero Palau
2025-04-10 11:37 ` Alejandro Lucero Palau
2025-04-04 16:11 ` Jonathan Cameron
2025-04-07 10:56 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 08/23] sfc: initialize dpa alejandro.lucero-palau
2025-04-04 16:12 ` Jonathan Cameron
2025-04-07 11:01 ` Alejandro Lucero Palau
2025-04-10 11:48 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 09/23] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-03-31 18:34 ` Simon Horman
2025-04-07 14:01 ` Alejandro Lucero Palau
2025-04-04 16:25 ` Jonathan Cameron
2025-04-11 21:07 ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 10/23] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 11/23] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-04-04 16:37 ` Jonathan Cameron
2025-04-07 13:25 ` Alejandro Lucero Palau
2025-04-11 21:30 ` Dave Jiang
2025-04-14 13:14 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 12/23] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-04-04 16:38 ` Jonathan Cameron
2025-04-07 11:02 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 13/23] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-04-04 16:41 ` Jonathan Cameron
2025-04-11 22:41 ` Dave Jiang
2025-04-14 13:28 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 14/23] sfc: get endpoint decoder alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 15/23] cxl: make region type based on endpoint type alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 16/23] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 17/23] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 18/23] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-04-04 16:45 ` Jonathan Cameron
2025-04-07 11:03 ` Alejandro Lucero Palau
2025-04-11 23:18 ` Dave Jiang
2025-04-14 13:52 ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 19/23] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-04-11 23:25 ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 20/23] sfc: create cxl region alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 21/23] cxl: add function for obtaining region range alejandro.lucero-palau
2025-04-11 23:32 ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 22/23] sfc: update MCDI protocol headers alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 23/23] sfc: support pio mapping based on cxl alejandro.lucero-palau
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