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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <alejandro.lucero-palau@amd.com>
Cc: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
	<dan.j.williams@intel.com>, <edward.cree@amd.com>,
	<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
	<edumazet@google.com>, <dave.jiang@intel.com>,
	Alejandro Lucero <alucerop@amd.com>,
	Ben Cheatham <benjamin.cheatham@amd.com>
Subject: Re: [PATCH v12 07/23] cxl: support dpa initialization without a mailbox
Date: Fri, 4 Apr 2025 17:11:46 +0100	[thread overview]
Message-ID: <20250404171146.00003258@huawei.com> (raw)
In-Reply-To: <20250331144555.1947819-8-alejandro.lucero-palau@amd.com>

On Mon, 31 Mar 2025 15:45:39 +0100
alejandro.lucero-palau@amd.com wrote:

> From: Alejandro Lucero <alucerop@amd.com>
> 
> Type3 relies on mailbox CXL_MBOX_OP_IDENTIFY command for initializing
> memdev state params which end up being used for dma initialization.
> 
> Allow a Type2 driver to initialize dpa simply by giving the size of its
> volatile and/or non-volatile hardware partitions.
> 
> Export cxl_dpa_setup as well for initializing those added dpa partitions
> with the proper resources.
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
> ---
>  drivers/cxl/core/mbox.c | 17 ++++++++++++++---
>  drivers/cxl/cxlmem.h    | 13 -------------
>  include/cxl/cxl.h       | 14 ++++++++++++++
>  3 files changed, 28 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index ab994d459f46..e4610e778723 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> @@ -1284,6 +1284,18 @@ static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_pa
>  	info->nr_partitions++;
>  }
>  
> +void cxl_mem_dpa_init(struct cxl_dpa_info *info, u64 volatile_bytes,
> +		      u64 persistent_bytes)
> +{
> +	if (!info->size)
> +		info->size = volatile_bytes + persistent_bytes;
> +
> +	add_part(info, 0, volatile_bytes, CXL_PARTMODE_RAM);
> +	add_part(info, volatile_bytes, persistent_bytes,
> +		 CXL_PARTMODE_PMEM);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_init, "CXL");
> +
>  int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
>  {
>  	struct cxl_dev_state *cxlds = &mds->cxlds;
> @@ -1298,9 +1310,8 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
>  	info->size = mds->total_bytes;
>  
>  	if (mds->partition_align_bytes == 0) {
> -		add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM);
> -		add_part(info, mds->volatile_only_bytes,
> -			 mds->persistent_only_bytes, CXL_PARTMODE_PMEM);
> +		cxl_mem_dpa_init(info, mds->volatile_only_bytes,
> +				 mds->persistent_only_bytes);

Why use this here but not a few lines later where the variant with
active_*_bytes are used?

>  		return 0;
>  	}
>  
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index e7cd31b9f107..e47f51025efd 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -98,19 +98,6 @@ int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
>  			 resource_size_t base, resource_size_t len,
>  			 resource_size_t skipped);
>  
> -#define CXL_NR_PARTITIONS_MAX 2
> -
> -struct cxl_dpa_info {
> -	u64 size;
> -	struct cxl_dpa_part_info {
> -		struct range range;
> -		enum cxl_partition_mode mode;
> -	} part[CXL_NR_PARTITIONS_MAX];
> -	int nr_partitions;
> -};
> -
> -int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info);
> -
>  static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
>  					 struct cxl_memdev *cxlmd)
>  {
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index a3cbf3a620e4..74f03773baed 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -213,6 +213,17 @@ struct cxl_dev_state {
>  #endif
>  };
>  
> +#define CXL_NR_PARTITIONS_MAX 2
> +
> +struct cxl_dpa_info {
> +	u64 size;
> +	struct cxl_dpa_part_info {
> +		struct range range;
> +		enum cxl_partition_mode mode;
> +	} part[CXL_NR_PARTITIONS_MAX];
> +	int nr_partitions;
> +};
> +
>  struct cxl_dev_state *_cxl_dev_state_create(struct device *dev,
>  					    enum cxl_devtype type, u64 serial,
>  					    u16 dvsec, size_t size,
> @@ -231,4 +242,7 @@ struct pci_dev;
>  struct cxl_memdev_state;
>  int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlmds,
>  			     unsigned long *caps);
> +void cxl_mem_dpa_init(struct cxl_dpa_info *info, u64 volatile_bytes,
> +		      u64 persistent_bytes);
> +int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info);
>  #endif


  parent reply	other threads:[~2025-04-04 16:11 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-31 14:45 [PATCH v12 00/23] cxl: add type2 device basic support alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 01/23] " alejandro.lucero-palau
2025-04-01 17:36   ` Alejandro Lucero Palau
2025-04-04 15:24   ` Jonathan Cameron
2025-04-07  9:50     ` Alejandro Lucero Palau
2025-04-10  8:12       ` Alejandro Lucero Palau
2025-04-07 16:55   ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 02/23] sfc: add cxl support alejandro.lucero-palau
2025-03-31 18:31   ` Simon Horman
2025-04-07 13:59     ` Alejandro Lucero Palau
2025-04-04 15:29   ` Jonathan Cameron
2025-03-31 14:45 ` [PATCH v12 03/23] cxl: move pci generic code alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 04/23] cxl: move register/capability check to driver alejandro.lucero-palau
2025-04-04 15:47   ` Jonathan Cameron
2025-04-07 13:40     ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 05/23] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-03-31 18:33   ` Simon Horman
2025-04-07 14:00     ` Alejandro Lucero Palau
2025-04-04 16:03   ` Jonathan Cameron
2025-04-07 10:04     ` Alejandro Lucero Palau
2025-04-15 16:34       ` Jonathan Cameron
2025-03-31 14:45 ` [PATCH v12 06/23] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 07/23] cxl: support dpa initialization without a mailbox alejandro.lucero-palau
2025-04-04 16:05   ` Jonathan Cameron
2025-04-07 10:53     ` Alejandro Lucero Palau
2025-04-10 11:37       ` Alejandro Lucero Palau
2025-04-04 16:11   ` Jonathan Cameron [this message]
2025-04-07 10:56     ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 08/23] sfc: initialize dpa alejandro.lucero-palau
2025-04-04 16:12   ` Jonathan Cameron
2025-04-07 11:01     ` Alejandro Lucero Palau
2025-04-10 11:48       ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 09/23] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-03-31 18:34   ` Simon Horman
2025-04-07 14:01     ` Alejandro Lucero Palau
2025-04-04 16:25   ` Jonathan Cameron
2025-04-11 21:07   ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 10/23] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 11/23] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-04-04 16:37   ` Jonathan Cameron
2025-04-07 13:25     ` Alejandro Lucero Palau
2025-04-11 21:30   ` Dave Jiang
2025-04-14 13:14     ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 12/23] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-04-04 16:38   ` Jonathan Cameron
2025-04-07 11:02     ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 13/23] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-04-04 16:41   ` Jonathan Cameron
2025-04-11 22:41   ` Dave Jiang
2025-04-14 13:28     ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 14/23] sfc: get endpoint decoder alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 15/23] cxl: make region type based on endpoint type alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 16/23] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 17/23] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 18/23] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-04-04 16:45   ` Jonathan Cameron
2025-04-07 11:03     ` Alejandro Lucero Palau
2025-04-11 23:18   ` Dave Jiang
2025-04-14 13:52     ` Alejandro Lucero Palau
2025-03-31 14:45 ` [PATCH v12 19/23] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-04-11 23:25   ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 20/23] sfc: create cxl region alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 21/23] cxl: add function for obtaining region range alejandro.lucero-palau
2025-04-11 23:32   ` Dave Jiang
2025-03-31 14:45 ` [PATCH v12 22/23] sfc: update MCDI protocol headers alejandro.lucero-palau
2025-03-31 14:45 ` [PATCH v12 23/23] sfc: support pio mapping based on cxl alejandro.lucero-palau

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