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From: Bjorn Helgaas <helgaas@kernel.org>
To: Manikandan Karunakaran Pillai <mpillai@cadence.com>
Cc: "bhelgaas@google.com" <bhelgaas@google.com>,
	"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
	"kw@linux.com" <kw@linux.com>,
	"manivannan.sadhasivam@linaro.org"
	<manivannan.sadhasivam@linaro.org>,
	"robh@kernel.org" <robh@kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: [PATCH 3/7] PCI: cadence: Add platform related architecture and register information
Date: Wed, 9 Apr 2025 17:09:32 -0500	[thread overview]
Message-ID: <20250409220932.GA299761@bhelgaas> (raw)
In-Reply-To: <CH2PPF4D26F8E1C5086A79888CB5AD0A01AA2A12@CH2PPF4D26F8E1C.namprd07.prod.outlook.com>

On Thu, Mar 27, 2025 at 11:39:43AM +0000, Manikandan Karunakaran Pillai wrote:
> Add the register bank offsets for different platforms and update the global
> platform data - platform architecture, EP or RP configuration and the
> correct values of register offsets for different register banks during the
> platform probe

Add period.

> @@ -72,6 +81,19 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
>  		rc = pci_host_bridge_priv(bridge);
>  		rc->pcie.dev = dev;
>  		rc->pcie.ops = &cdns_plat_ops;
> +		rc->pcie.is_hpa = data->is_hpa;
> +		/*

Add a blank line between the code and the start of the comment.

> +		 * Store all the register bank offsets
> +		 */
> +		rc->pcie.cdns_pcie_reg_offsets.ip_reg_bank_off = data->ip_reg_bank_off;
> +		rc->pcie.cdns_pcie_reg_offsets.ip_cfg_ctrl_reg_off = data->ip_cfg_ctrl_reg_off;
> +		rc->pcie.cdns_pcie_reg_offsets.axi_mstr_common_off = data->axi_mstr_common_off;
> +		rc->pcie.cdns_pcie_reg_offsets.axi_master_off = data->axi_master_off;
> +		rc->pcie.cdns_pcie_reg_offsets.axi_slave_off = data->axi_slave_off;
> +		rc->pcie.cdns_pcie_reg_offsets.axi_hls_off = data->axi_hls_off;
> +		rc->pcie.cdns_pcie_reg_offsets.axi_ras_off = data->axi_ras_off;
> +		rc->pcie.cdns_pcie_reg_offsets.axi_dti_off = data->axi_dti_off;

But what's the point of copying all these offsets?  Can't you just
keep the offsets in a couple separate structures and save the pointer?

It looks like cdns_plat_pcie_host_of_data and
cdns_plat_pcie_ep_of_data could use the same pointer, as could
cdns_plat_pcie_hpa_host_of_data and cdns_plat_pcie_hpa_ep_of_data.

> @@ -99,6 +121,19 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
>  
>  		ep->pcie.dev = dev;
>  		ep->pcie.ops = &cdns_plat_ops;
> +		ep->pcie.is_hpa = data->is_hpa;
> +		/*

Add blank line again.

> +		 * Store all the register bank offset

>  static const struct cdns_plat_pcie_of_data cdns_plat_pcie_host_of_data = {
>  	.is_rc = true,
> +	.is_hpa = false,
> +	.ip_reg_bank_off = 0x0,
> +	.ip_cfg_ctrl_reg_off = 0x0,
> +	.axi_mstr_common_off = 0x0,
> +	.axi_slave_off = 0x0,
> +	.axi_master_off = 0x0,
> +	.axi_hls_off = 0x0,
> +	.axi_ras_off = 0x0,
> +	.axi_dti_off = 0x0,

In my opinion, you should only initialize fields that are non-false
and non-zero.  Then the differences are more obvious.

Bjorn

  reply	other threads:[~2025-04-09 22:09 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20250327105429.2947013-1-mpillai@cadence.com>
2025-03-27 10:59 ` [PATCH 0/7] Enhance the PCIe controller driver Manikandan Karunakaran Pillai
     [not found]   ` <20250327111106.2947888-1-mpillai@cadence.com>
2025-03-27 11:19     ` [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations Manikandan Karunakaran Pillai
2025-03-27 14:15       ` Krzysztof Kozlowski
2025-03-28  5:07         ` Manikandan Karunakaran Pillai
2025-03-28  7:20           ` Krzysztof Kozlowski
2025-03-28  8:22       ` Krzysztof Kozlowski
2025-03-28  8:48         ` Hans Zhang
2025-03-28  9:17           ` Krzysztof Kozlowski
2025-03-30 14:59             ` Hans Zhang
     [not found]   ` <20250327111127.2947944-1-mpillai@cadence.com>
2025-03-27 11:26     ` [PATCH 2/7] PCI: cadence: Add header support for PCIe next generation controllers Manikandan Karunakaran Pillai
2025-03-27 12:01       ` Hans Zhang
2025-04-09 20:39       ` Bjorn Helgaas
2025-04-11  4:16         ` Manikandan Karunakaran Pillai
     [not found]   ` <20250327111146.2948015-1-mpillai@cadence.com>
2025-03-27 11:39     ` [PATCH 3/7] PCI: cadence: Add platform related architecture and register information Manikandan Karunakaran Pillai
2025-04-09 22:09       ` Bjorn Helgaas [this message]
2025-04-11  4:21         ` Manikandan Karunakaran Pillai
     [not found]   ` <20250327111200.2948071-1-mpillai@cadence.com>
2025-03-27 11:40     ` [PATCH 4/7] PCI: cadence: Add support for PCIe Endpoint HPA controllers Manikandan Karunakaran Pillai
2025-04-09 22:15       ` Bjorn Helgaas
2025-04-11  4:23         ` Manikandan Karunakaran Pillai
     [not found]   ` <20250327111222.2948127-1-mpillai@cadence.com>
2025-03-27 11:41     ` [PATCH 5/7] PCI: cadence: Update the PCIe controller register address offsets Manikandan Karunakaran Pillai
2025-04-09 20:18       ` Bjorn Helgaas
2025-04-11  4:11         ` Manikandan Karunakaran Pillai
     [not found]   ` <20250327111241.2948184-1-mpillai@cadence.com>
2025-03-27 11:42     ` [PATCH 6/7] PCI: cadence: Add callback functions for Root Port and EP controller Manikandan Karunakaran Pillai
2025-04-09 22:45       ` Bjorn Helgaas
2025-04-11  4:26         ` Manikandan Karunakaran Pillai
     [not found]   ` <20250327111256.2948250-1-mpillai@cadence.com>
2025-03-27 11:43     ` [PATCH 7/7] PCI: cadence: Update support for TI J721e boards Manikandan Karunakaran Pillai
2025-03-27 12:03   ` [PATCH 0/7] Enhance the PCIe controller driver Hans Zhang
2025-03-27 14:16   ` Krzysztof Kozlowski
2025-03-27 14:43     ` Manikandan Karunakaran Pillai
2025-03-27 14:46       ` Krzysztof Kozlowski
2025-04-09 17:08   ` manivannan.sadhasivam
2025-04-11  4:08     ` Manikandan Karunakaran Pillai
2025-04-09 20:11   ` Bjorn Helgaas
2025-04-11  4:10     ` Manikandan Karunakaran Pillai

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