From: Krzysztof Kozlowski <krzk@kernel.org>
To: Hans Zhang <hans.zhang@cixtech.com>,
Manikandan Karunakaran Pillai <mpillai@cadence.com>
Cc: "bhelgaas@google.com" <bhelgaas@google.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
"kw@linux.com" <kw@linux.com>,
"manivannan.sadhasivam@linaro.org"
<manivannan.sadhasivam@linaro.org>,
"robh@kernel.org" <robh@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations
Date: Fri, 28 Mar 2025 10:17:59 +0100 [thread overview]
Message-ID: <d275cfe1-db7e-47d6-9ec6-b36f13524d65@kernel.org> (raw)
In-Reply-To: <4bcc07b1-00ce-4ff9-bf23-e06b78950026@cixtech.com>
On 28/03/2025 09:48, Hans Zhang wrote:
>
>
> On 2025/3/28 16:22, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL
>>
>> On Thu, Mar 27, 2025 at 11:19:47AM +0000, Manikandan Karunakaran Pillai wrote:
>>> Document the compatible property for the newly added values for PCIe EP and
>>> RP configurations. Fix the compilation issues that came up for the existing
>>> Cadence bindings
>>>
>>> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
>>> ---
>>> .../bindings/pci/cdns,cdns-pcie-ep.yaml | 12 +-
>>> .../bindings/pci/cdns,cdns-pcie-host.yaml | 119 +++++++++++++++---
>>> 2 files changed, 110 insertions(+), 21 deletions(-)
>>
>> One more thing: SoB mismatch. Maybe got corrupted by Microsoft (it is
>> known), so you really need to fix your mailing setup or use b4 relay.
>>
>
> Hi Krzysztof,
>
> I have obtained Manikandan's consent and we will collaborate to submit
It does not matter. You still need proper SoB / DCO chain. Please follow
submitting patches.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-03-28 9:18 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20250327105429.2947013-1-mpillai@cadence.com>
2025-03-27 10:59 ` [PATCH 0/7] Enhance the PCIe controller driver Manikandan Karunakaran Pillai
[not found] ` <20250327111106.2947888-1-mpillai@cadence.com>
2025-03-27 11:19 ` [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations Manikandan Karunakaran Pillai
2025-03-27 14:15 ` Krzysztof Kozlowski
2025-03-28 5:07 ` Manikandan Karunakaran Pillai
2025-03-28 7:20 ` Krzysztof Kozlowski
2025-03-28 8:22 ` Krzysztof Kozlowski
2025-03-28 8:48 ` Hans Zhang
2025-03-28 9:17 ` Krzysztof Kozlowski [this message]
2025-03-30 14:59 ` Hans Zhang
[not found] ` <20250327111127.2947944-1-mpillai@cadence.com>
2025-03-27 11:26 ` [PATCH 2/7] PCI: cadence: Add header support for PCIe next generation controllers Manikandan Karunakaran Pillai
2025-03-27 12:01 ` Hans Zhang
2025-04-09 20:39 ` Bjorn Helgaas
2025-04-11 4:16 ` Manikandan Karunakaran Pillai
[not found] ` <20250327111146.2948015-1-mpillai@cadence.com>
2025-03-27 11:39 ` [PATCH 3/7] PCI: cadence: Add platform related architecture and register information Manikandan Karunakaran Pillai
2025-04-09 22:09 ` Bjorn Helgaas
2025-04-11 4:21 ` Manikandan Karunakaran Pillai
[not found] ` <20250327111200.2948071-1-mpillai@cadence.com>
2025-03-27 11:40 ` [PATCH 4/7] PCI: cadence: Add support for PCIe Endpoint HPA controllers Manikandan Karunakaran Pillai
2025-04-09 22:15 ` Bjorn Helgaas
2025-04-11 4:23 ` Manikandan Karunakaran Pillai
[not found] ` <20250327111222.2948127-1-mpillai@cadence.com>
2025-03-27 11:41 ` [PATCH 5/7] PCI: cadence: Update the PCIe controller register address offsets Manikandan Karunakaran Pillai
2025-04-09 20:18 ` Bjorn Helgaas
2025-04-11 4:11 ` Manikandan Karunakaran Pillai
[not found] ` <20250327111241.2948184-1-mpillai@cadence.com>
2025-03-27 11:42 ` [PATCH 6/7] PCI: cadence: Add callback functions for Root Port and EP controller Manikandan Karunakaran Pillai
2025-04-09 22:45 ` Bjorn Helgaas
2025-04-11 4:26 ` Manikandan Karunakaran Pillai
[not found] ` <20250327111256.2948250-1-mpillai@cadence.com>
2025-03-27 11:43 ` [PATCH 7/7] PCI: cadence: Update support for TI J721e boards Manikandan Karunakaran Pillai
2025-03-27 12:03 ` [PATCH 0/7] Enhance the PCIe controller driver Hans Zhang
2025-03-27 14:16 ` Krzysztof Kozlowski
2025-03-27 14:43 ` Manikandan Karunakaran Pillai
2025-03-27 14:46 ` Krzysztof Kozlowski
2025-04-09 17:08 ` manivannan.sadhasivam
2025-04-11 4:08 ` Manikandan Karunakaran Pillai
2025-04-09 20:11 ` Bjorn Helgaas
2025-04-11 4:10 ` Manikandan Karunakaran Pillai
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