[PATCH] x86/cpufeatures: Clean up formatting

[PATCH] x86/cpufeatures: Clean up formatting

[Borislav Petkov]

From: "Borislav Petkov (AMD)" <bp@alien8.de>

It is a special file with special formatting so remove one whitespace
damage and format newer defines like the rest.

No functional changes.

Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
---
 arch/x86/include/asm/cpufeatures.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 6c2c152d8a67..6ff634304fb1 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -477,10 +477,10 @@
 #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
 #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
 #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
-#define X86_FEATURE_AMD_FAST_CPPC	(21*32 + 5) /* Fast CPPC */
-#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
-#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
-#define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
+#define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */
+#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32+ 6) /* Heterogeneous Core Topology */
+#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */
+#define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */
 
 /*
  * BUG word(s)
@@ -527,10 +527,10 @@
 #define X86_BUG_TDX_PW_MCE		X86_BUG(31) /* "tdx_pw_mce" CPU may incur #MC if non-TD software does partial write to TDX private memory */
 
 /* BUG word 2 */
-#define X86_BUG_SRSO			X86_BUG(1*32 + 0) /* "srso" AMD SRSO bug */
-#define X86_BUG_DIV0			X86_BUG(1*32 + 1) /* "div0" AMD DIV0 speculation bug */
-#define X86_BUG_RFDS			X86_BUG(1*32 + 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
-#define X86_BUG_BHI			X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch History Injection */
-#define X86_BUG_IBPB_NO_RET	   	X86_BUG(1*32 + 4) /* "ibpb_no_ret" IBPB omits return target predictions */
-#define X86_BUG_SPECTRE_V2_USER		X86_BUG(1*32 + 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
+#define X86_BUG_SRSO			X86_BUG( 1*32+ 0) /* "srso" AMD SRSO bug */
+#define X86_BUG_DIV0			X86_BUG( 1*32+ 1) /* "div0" AMD DIV0 speculation bug */
+#define X86_BUG_RFDS			X86_BUG( 1*32+ 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
+#define X86_BUG_BHI			X86_BUG( 1*32+ 3) /* "bhi" CPU is affected by Branch History Injection */
+#define X86_BUG_IBPB_NO_RET		X86_BUG( 1*32+ 4) /* "ibpb_no_ret" IBPB omits return target predictions */
+#define X86_BUG_SPECTRE_V2_USER		X86_BUG( 1*32+ 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
 #endif /* _ASM_X86_CPUFEATURES_H */
-- 
2.43.0

Re: [PATCH] x86/cpufeatures: Clean up formatting

[Xin Li]

On 4/10/2025 9:54 AM, Borislav Petkov wrote:
> @@ -477,10 +477,10 @@
>   #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
>   #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
>   #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
> -#define X86_FEATURE_AMD_FAST_CPPC	(21*32 + 5) /* Fast CPPC */
> -#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
> -#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
> -#define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
> +#define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */
> +#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32+ 6) /* Heterogeneous Core Topology */
> +#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */
> +#define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */

Ha, I did a similar cleanup with adding the immediate MSR instruction
support (you asked to use scattered):

https://lore.kernel.org/lkml/20250331082251.3171276-9-xin@zytor.com/

Thanks!
     Xin

Re: [PATCH] x86/cpufeatures: Clean up formatting

[Borislav Petkov]

On Thu, Apr 10, 2025 at 10:11:56AM -0700, Xin Li wrote:
> On 4/10/2025 9:54 AM, Borislav Petkov wrote:
> > @@ -477,10 +477,10 @@
> >   #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
> >   #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
> >   #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
> > -#define X86_FEATURE_AMD_FAST_CPPC	(21*32 + 5) /* Fast CPPC */
> > -#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
> > -#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
> > -#define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
> > +#define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */
> > +#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32+ 6) /* Heterogeneous Core Topology */
> > +#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */
> > +#define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */
> 
> Ha, I did a similar cleanup with adding the immediate MSR instruction
> support (you asked to use scattered):
> 
> https://lore.kernel.org/lkml/20250331082251.3171276-9-xin@zytor.com/

Except you're moving the numbers one column to the right while the other
columns remain at that indentation.

Instead of re-tabulating that whole file, I think we should simply shorten
those

X86_FEATURE_AMD_HETEROGENEOUS_CORES and X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT

straddlers.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH] x86/cpufeatures: Clean up formatting

[Xin Li]

On 4/10/2025 10:25 AM, Borislav Petkov wrote:
> On Thu, Apr 10, 2025 at 10:11:56AM -0700, Xin Li wrote:
>> On 4/10/2025 9:54 AM, Borislav Petkov wrote:
>>> @@ -477,10 +477,10 @@
>>>    #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
>>>    #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
>>>    #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
>>> -#define X86_FEATURE_AMD_FAST_CPPC	(21*32 + 5) /* Fast CPPC */
>>> -#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
>>> -#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
>>> -#define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
>>> +#define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */
>>> +#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32+ 6) /* Heterogeneous Core Topology */
>>> +#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */
>>> +#define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */
>>
>> Ha, I did a similar cleanup with adding the immediate MSR instruction
>> support (you asked to use scattered):
>>
>> https://lore.kernel.org/lkml/20250331082251.3171276-9-xin@zytor.com/
> 
> Except you're moving the numbers one column to the right while the other
> columns remain at that indentation.
> 
> Instead of re-tabulating that whole file, I think we should simply shorten
> those
> 
> X86_FEATURE_AMD_HETEROGENEOUS_CORES and X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT
> 
> straddlers.

Good idea.

I ever had a patch in which the last column of the same type macros are
not aligned and tglx asked me to make them aligned.  But that didn't
need any name shortened.

Thanks!
     Xin

Re: [PATCH] x86/cpufeatures: Clean up formatting

[Borislav Petkov]

On Thu, Apr 10, 2025 at 10:52:56AM -0700, Xin Li wrote:
> I ever had a patch in which the last column of the same type macros are
> not aligned and tglx asked me to make them aligned.  But that didn't
> need any name shortened.

If you wanna, You can take mine, and then do two more patches ontop,
shortening one name in each one.

:-)

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH] x86/cpufeatures: Clean up formatting

[Xin Li]

On Apr 10, 2025, at 11:07 AM, Borislav Petkov <bp@alien8.de> wrote:
> 
> On Thu, Apr 10, 2025 at 10:52:56AM -0700, Xin Li wrote:
>> I ever had a patch in which the last column of the same type macros are
>> not aligned and tglx asked me to make them aligned.  But that didn't
>> need any name shortened.
> 
> If you wanna, You can take mine, and then do two more patches ontop,
> shortening one name in each one.
> 
> :-)

Sure :)