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From: Aleksandr Shubin <privatesub2@gmail.com>
To: linux-kernel@vger.kernel.org
Cc: "Aleksandr Shubin" <privatesub2@gmail.com>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Uwe Kleine-König" <ukleinek@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Samuel Holland" <samuel@sholland.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Cheo Fusi" <fusibrandon13@gmail.com>,
	linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org
Subject: [PATCH v12 3/3] riscv: dts: allwinner: d1: Add pwm node
Date: Sun, 27 Apr 2025 17:24:55 +0300	[thread overview]
Message-ID: <20250427142500.151925-4-privatesub2@gmail.com> (raw)
In-Reply-To: <20250427142500.151925-1-privatesub2@gmail.com>

D1 and T113s contain a pwm controller with 8 channels.
This controller is supported by the sun20i-pwm driver.

Add a device tree node for it.

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com>
---
 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index e4175adb028d..2c26cb8b2b07 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -145,6 +145,18 @@ uart3_pb_pins: uart3-pb-pins {
 			};
 		};
 
+		pwm: pwm@2000c00 {
+			compatible = "allwinner,sun20i-d1-pwm";
+			reg = <0x02000c00 0x400>;
+			clocks = <&ccu CLK_BUS_PWM>,
+				 <&dcxo>,
+				 <&ccu CLK_APB0>;
+			clock-names = "bus", "hosc", "apb";
+			resets = <&ccu RST_BUS_PWM>;
+			status = "disabled";
+			#pwm-cells = <0x3>;
+		};
+
 		ccu: clock-controller@2001000 {
 			compatible = "allwinner,sun20i-d1-ccu";
 			reg = <0x2001000 0x1000>;
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: Aleksandr Shubin <privatesub2@gmail.com>
To: linux-kernel@vger.kernel.org
Cc: "Aleksandr Shubin" <privatesub2@gmail.com>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Uwe Kleine-König" <ukleinek@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Samuel Holland" <samuel@sholland.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Cheo Fusi" <fusibrandon13@gmail.com>,
	linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org
Subject: [PATCH v12 3/3] riscv: dts: allwinner: d1: Add pwm node
Date: Sun, 27 Apr 2025 17:24:55 +0300	[thread overview]
Message-ID: <20250427142500.151925-4-privatesub2@gmail.com> (raw)
In-Reply-To: <20250427142500.151925-1-privatesub2@gmail.com>

D1 and T113s contain a pwm controller with 8 channels.
This controller is supported by the sun20i-pwm driver.

Add a device tree node for it.

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com>
---
 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index e4175adb028d..2c26cb8b2b07 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -145,6 +145,18 @@ uart3_pb_pins: uart3-pb-pins {
 			};
 		};
 
+		pwm: pwm@2000c00 {
+			compatible = "allwinner,sun20i-d1-pwm";
+			reg = <0x02000c00 0x400>;
+			clocks = <&ccu CLK_BUS_PWM>,
+				 <&dcxo>,
+				 <&ccu CLK_APB0>;
+			clock-names = "bus", "hosc", "apb";
+			resets = <&ccu RST_BUS_PWM>;
+			status = "disabled";
+			#pwm-cells = <0x3>;
+		};
+
 		ccu: clock-controller@2001000 {
 			compatible = "allwinner,sun20i-d1-ccu";
 			reg = <0x2001000 0x1000>;
-- 
2.25.1


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  parent reply	other threads:[~2025-04-27 14:33 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-27 14:24 [PATCH v12 0/3] Add support for Allwinner PWM on D1/T113s/R329 SoCs Aleksandr Shubin
2025-04-27 14:24 ` Aleksandr Shubin
2025-04-27 14:24 ` [PATCH v12 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller Aleksandr Shubin
2025-04-27 14:24   ` Aleksandr Shubin
2025-05-12 22:56   ` Andre Przywara
2025-05-12 22:56     ` Andre Przywara
2025-06-19  9:44     ` Alexandre Belloni
2025-06-19  9:44       ` Alexandre Belloni
2025-06-19 12:10       ` Andre Przywara
2025-06-19 12:10         ` Andre Przywara
2025-07-31 10:00         ` Uwe Kleine-König
2025-07-31 10:00           ` Uwe Kleine-König
2025-04-27 14:24 ` [PATCH v12 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support Aleksandr Shubin
2025-04-27 14:24   ` Aleksandr Shubin
2025-05-12 22:39   ` Andre Przywara
2025-05-12 22:39     ` Andre Przywara
2025-05-24  9:07     ` Александр Шубин
2025-05-24  9:07       ` Александр Шубин
2025-05-28 11:08       ` Uwe Kleine-König
2025-05-28 11:08         ` Uwe Kleine-König
2025-05-28 12:29         ` Andre Przywara
2025-05-28 12:29           ` Andre Przywara
2025-06-18 18:19           ` Uwe Kleine-König
2025-06-18 18:19             ` Uwe Kleine-König
2025-04-27 14:24 ` Aleksandr Shubin [this message]
2025-04-27 14:24   ` [PATCH v12 3/3] riscv: dts: allwinner: d1: Add pwm node Aleksandr Shubin
2026-01-22 16:43 ` [PATCH v12 0/3] Add support for Allwinner PWM on D1/T113s/R329 SoCs Paul Kocialkowski
2026-01-22 16:43   ` Paul Kocialkowski
2026-01-28 16:52   ` Александр Шубин
2026-01-28 16:52     ` Александр Шубин

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