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From: E Shattow <e@freeshell.de>
To: Conor Dooley <conor@kernel.org>,
	Emil Renner Berthing <kernel@esmil.dk>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, E Shattow <e@freeshell.de>
Subject: [PATCH v3 1/4] riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
Date: Fri,  2 May 2025 03:30:41 -0700	[thread overview]
Message-ID: <20250502103101.957016-2-e@freeshell.de> (raw)
In-Reply-To: <20250502103101.957016-1-e@freeshell.de>

Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
boot loader before kernel.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index c2f70f5e2918..f1489e9bb83e 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -353,9 +353,17 @@ &spi0 {
 };
 
 &syscrg {
-	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
+	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
+			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
 			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
-	assigned-clock-rates = <500000000>, <1500000000>;
+	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
 };
 
 &sysgpio {
-- 
2.49.0


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WARNING: multiple messages have this Message-ID (diff)
From: E Shattow <e@freeshell.de>
To: Conor Dooley <conor@kernel.org>,
	Emil Renner Berthing <kernel@esmil.dk>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, E Shattow <e@freeshell.de>
Subject: [PATCH v3 1/4] riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
Date: Fri,  2 May 2025 03:30:41 -0700	[thread overview]
Message-ID: <20250502103101.957016-2-e@freeshell.de> (raw)
In-Reply-To: <20250502103101.957016-1-e@freeshell.de>

Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
boot loader before kernel.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index c2f70f5e2918..f1489e9bb83e 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -353,9 +353,17 @@ &spi0 {
 };
 
 &syscrg {
-	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
+	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
+			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
 			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
-	assigned-clock-rates = <500000000>, <1500000000>;
+	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
 };
 
 &sysgpio {
-- 
2.49.0


  reply	other threads:[~2025-05-02 10:33 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-02 10:30 [PATCH v3 0/4] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes E Shattow
2025-05-02 10:30 ` E Shattow
2025-05-02 10:30 ` E Shattow [this message]
2025-05-02 10:30   ` [PATCH v3 1/4] riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg E Shattow
2025-05-15 17:09   ` Emil Renner Berthing
2025-05-15 17:09     ` Emil Renner Berthing
2025-05-02 10:30 ` [PATCH v3 2/4] riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz E Shattow
2025-05-02 10:30   ` E Shattow
2025-05-15 17:09   ` Emil Renner Berthing
2025-05-15 17:09     ` Emil Renner Berthing
2025-05-02 10:30 ` [PATCH v3 3/4] riscv: dts: starfive: jh7110-common: add eeprom node to i2c5 E Shattow
2025-05-02 10:30   ` E Shattow
2025-05-02 10:30 ` [PATCH v3 4/4] riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader E Shattow
2025-05-02 10:30   ` E Shattow
2025-05-15 17:10   ` Emil Renner Berthing
2025-05-15 17:10     ` Emil Renner Berthing
2025-05-15 17:10 ` [PATCH v3 0/4] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes Emil Renner Berthing
2025-05-15 17:10   ` Emil Renner Berthing
2025-05-15 21:08 ` Conor Dooley
2025-05-15 21:08   ` Conor Dooley

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