* [PATCH v5 3/3] arm64: dts: ti: k3-am62l: add initial reference board file
2025-05-08 3:09 [PATCH v5 0/3] arm64: dts: ti: introduce basic support for the AM62L Bryan Brattlof
@ 2025-05-08 3:09 ` Bryan Brattlof
0 siblings, 0 replies; 2+ messages in thread
From: Bryan Brattlof @ 2025-05-08 3:09 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Bryan Brattlof
From: Vignesh Raghavendra <vigneshr@ti.com>
Add the initial board file for the AM62L3's Evaluation Module.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
---
Changes from v1:
- switched to non-direct links so TRM updates are automatic
- removed current-speed property from main_uart0
- removed empty reserved-memory{} node
- removed serial2 from aliases{} node
- corrected main_uart0 pinmux
Changes from v2:
- alphabetized phandles
- corrected macros and node names for main_uart0 pinmux node
Changes from v3:
- added and enabled more nodes that have been validated
- added link to data sheet which is now public
Changes in v4:
- Corrected Copyright year
---
arch/arm64/boot/dts/ti/k3-am62l3-evm.dts | 294 +++++++++++++++++++++++++++++++
1 file changed, 294 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts
new file mode 100644
index 0000000000000..16efb60bf3260
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/*
+ * Device Tree file for the AM62L3 Evaluation Module
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
+ * Data Sheet: https://www.ti.com/lit/pdf/sprspa1
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "k3-am62l3.dtsi"
+#include "k3-pinctrl.h"
+
+/ {
+ compatible = "ti,am62l3-evm", "ti,am62l3";
+ model = "Texas Instruments AM62L3 Evaluation Module";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usr_btn_pins_default>;
+
+ usr: button-usr {
+ label = "User Key";
+ linux,code = <BTN_0>;
+ gpios = <&gpio0 90 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usr_led_pins_default>;
+
+ led-0 {
+ label = "am62-sk:green:heartbeat";
+ gpios = <&gpio0 123 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ default-state = "on";
+ };
+ };
+
+ memory@80000000 {
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ device_type = "memory";
+ bootph-all;
+ };
+
+ vcc_1v8: regulator-3 {
+ /* output of TPS6282518DMQ */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3_sys>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_3v3_sys: regulator-1 {
+ /* output of LM61460-Q1 */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vmain_pd>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vmain_pd: regulator-0 {
+ /* TPS65988 PD CONTROLLER OUTPUT */
+ bootph-all;
+ compatible = "regulator-fixed";
+ regulator-name = "vmain_pd";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+ bootph-all;
+
+ eeprom@51 {
+ /* AT24C512C-MAHM-T or M24512-DFMC6TG */
+ compatible = "atmel,24c512";
+ reg = <0x51>;
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins_default>;
+ pinctrl-names = "default";
+ clock-frequency = <100000>;
+ status = "okay";
+ bootph-all;
+
+ exp1: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "", "",
+ "UART1_FET_SEL", "MMC1_SD_EN",
+ "VPP_EN", "EXP_PS_3V3_EN",
+ "UART1_FET_BUF_EN", "",
+ "DSI_GPIO0", "DSI_GPIO1",
+ "", "BT_UART_WAKE_SOC_3V3",
+ "USB_TYPEA_OC_INDICATION", "",
+ "", "WLAN_ALERTn",
+ "HDMI_INTn", "TEST_GPIO2",
+ "MCASP0_FET_EN", "MCASP0_BUF_BT_EN",
+ "MCASP0_FET_SEL", "DSI_EDID",
+ "PD_I2C_IRQ", "IO_EXP_TEST_LED";
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <91 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ pinctrl-0 = <&gpio0_ioexp_intr_pins_default>;
+ pinctrl-names = "default";
+ bootph-all;
+ };
+
+ exp2: gpio@23 {
+ compatible = "ti,tca6424";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "BT_EN_SOC", "VOUT0_FET_SEL0",
+ "", "",
+ "", "",
+ "", "",
+ "WL_LT_EN", "EXP_PS_5V0_EN",
+ "TP45", "TP48",
+ "TP46", "TP49",
+ "TP47", "TP50",
+ "GPIO_QSPI_NAND_RSTn", "GPIO_HDMI_RSTn",
+ "GPIO_CPSW1_RST", "GPIO_CPSW2_RST",
+ "", "GPIO_AUD_RSTn",
+ "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST";
+
+ bootph-all;
+ };
+};
+
+&pmx0 {
+ gpio0_ioexp_intr_pins_default: gpio0-ioexp-intr-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x01b0, PIN_INPUT, 7) /* (B12) SPI0_D1.GPIO0_91 */
+ >;
+ bootph-all;
+ };
+
+ i2c0_pins_default: i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x01cc, PIN_INPUT_PULLUP, 0) /* (B7) I2C0_SCL */
+ AM62LX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 0) /* (A7) I2C0_SDA */
+ >;
+ bootph-all;
+ };
+
+ i2c1_pins_default: i2c1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 0) /* (D7) I2C1_SCL */
+ AM62LX_IOPAD(0x01d8, PIN_INPUT_PULLUP, 0) /* (A6) I2C1_SDA */
+ >;
+ };
+
+ mmc0_pins_default: mmc0-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (D2) MMC0_CMD */
+ AM62LX_IOPAD(0x020c, PIN_OUTPUT, 0) /* (B2) MMC0_CLK */
+ AM62LX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (D3) MMC0_DAT0 */
+ AM62LX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (D4) MMC0_DAT1 */
+ AM62LX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (C1) MMC0_DAT2 */
+ AM62LX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (C2) MMC0_DAT3 */
+ AM62LX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (C4) MMC0_DAT4 */
+ AM62LX_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (B3) MMC0_DAT5 */
+ AM62LX_IOPAD(0x01f0, PIN_INPUT_PULLUP, 0) /* (A3) MMC0_DAT6 */
+ AM62LX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B4) MMC0_DAT7 */
+ >;
+ bootph-all;
+ };
+
+ mmc1_pins_default: mmc1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */
+ AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */
+ AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */
+ AM62LX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y4) MMC1_DAT1 */
+ AM62LX_IOPAD(0x021c, PIN_INPUT_PULLUP, 0) /* (AA2) MMC1_DAT2 */
+ AM62LX_IOPAD(0x0218, PIN_INPUT_PULLUP, 0) /* (AB2) MMC1_DAT3 */
+ AM62LX_IOPAD(0x0234, PIN_INPUT, 0) /* (B6) MMC1_SDCD */
+ >;
+ bootph-all;
+ };
+
+ uart0_pins_default: uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */
+ AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */
+ >;
+ bootph-all;
+ };
+
+ uart1_pins_default: uart1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0180, PIN_INPUT, 2) /* (A8) MCASP0_AXR3.UART1_CTSn */
+ AM62LX_IOPAD(0x0184, PIN_OUTPUT, 2) /* (B10) MCASP0_AXR2.UART1_RTSn */
+ AM62LX_IOPAD(0x0198, PIN_INPUT, 2) /* (C11) MCASP0_AFSR.UART1_RXD */
+ AM62LX_IOPAD(0x019c, PIN_OUTPUT, 2) /* (A12) MCASP0_ACLKR.UART1_TXD */
+ >;
+ bootph-all;
+ };
+
+ usb1_default_pins: usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (A5) USB1_DRVVBUS */
+ >;
+ };
+
+ usr_btn_pins_default: usr-btn-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x01ac, PIN_INPUT, 7) /* (E12) SPI0_D0.GPIO0_90 */
+ >;
+ };
+
+ usr_led_pins_default: usr-led-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0238, PIN_OUTPUT, 7) /* (D24) MMC1_SDWP.GPIO0_123 */
+ >;
+ };
+};
+
+&sdhci0 {
+ /* eMMC */
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-names = "default";
+ non-removable;
+ status = "okay";
+ bootph-all;
+};
+
+&sdhci1 {
+ /* SD/MMC */
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ bootph-all;
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ bootph-all;
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ bootph-all;
+};
+
+&usb1 {
+ pinctrl-0 = <&usb1_default_pins>;
+ pinctrl-names = "default";
+ dr_mode = "host";
+};
+
+&usbss1 {
+ ti,vbus-divider;
+ status = "okay";
+};
--
2.49.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v5 3/3] arm64: dts: ti: k3-am62l: add initial reference board file
@ 2025-05-09 14:55 kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2025-05-09 14:55 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250507-am62lx-v5-3-4b57ea878e62@ti.com>
References: <20250507-am62lx-v5-3-4b57ea878e62@ti.com>
TO: Bryan Brattlof <bb@ti.com>
TO: Nishanth Menon <nm@ti.com>
TO: Vignesh Raghavendra <vigneshr@ti.com>
TO: Tero Kristo <kristo@kernel.org>
TO: Rob Herring <robh@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Conor Dooley <conor+dt@kernel.org>
CC: linux-arm-kernel@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: Bryan Brattlof <bb@ti.com>
Hi Bryan,
kernel test robot noticed the following build warnings:
[auto build test WARNING on ed6f779e213070572e53e9801e4a6e510d7bc208]
url: https://github.com/intel-lab-lkp/linux/commits/Bryan-Brattlof/dt-bindings-arm-ti-Add-binding-for-AM62L-SoCs/20250508-111107
base: ed6f779e213070572e53e9801e4a6e510d7bc208
patch link: https://lore.kernel.org/r/20250507-am62lx-v5-3-4b57ea878e62%40ti.com
patch subject: [PATCH v5 3/3] arm64: dts: ti: k3-am62l: add initial reference board file
:::::: branch date: 2 days ago
:::::: commit date: 2 days ago
config: arm64-randconfig-001-20250509 (https://download.01.org/0day-ci/archive/20250509/202505092201.vuNUBwFc-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 7.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250509/202505092201.vuNUBwFc-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202505092201.vuNUBwFc-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> arch/arm64/boot/dts/ti/k3-am62l.dtsi:101.30-113.5: Warning (simple_bus_reg): /bus@f0000/bus@43000000: simple-bus unit address format error, expected "a80000"
>> arch/arm64/boot/dts/ti/k3-am62l-main.dtsi:232.19-256.4: Warning (simple_bus_reg): /bus@f0000/bus@fc00000: simple-bus unit address format error, expected "100"
vim +/a80000 +101 arch/arm64/boot/dts/ti/k3-am62l.dtsi
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 14
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 15 / {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 16 model = "Texas Instruments K3 AM62L3 SoC";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 17 compatible = "ti,am62l3";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 18 interrupt-parent = <&gic500>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 19 #address-cells = <2>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 20 #size-cells = <2>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 21
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 22 firmware {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 23 optee {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 24 compatible = "linaro,optee-tz";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 25 method = "smc";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 26 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 27
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 28 psci: psci {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 29 compatible = "arm,psci-1.0";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 30 method = "smc";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 31 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 32
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 33 scmi: scmi {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 34 compatible = "arm,scmi-smc";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 35 arm,smc-id = <0x82004000>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 36 shmem = <&scmi_shmem>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 37 #address-cells = <1>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 38 #size-cells = <0>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 39
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 40 scmi_clk: protocol@14 {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 41 reg = <0x14>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 42 #clock-cells = <1>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 43 bootph-all;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 44 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 45
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 46 scmi_pds: protocol@11 {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 47 reg = <0x11>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 48 #power-domain-cells = <1>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 49 bootph-all;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 50 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 51 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 52 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 53
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 54 a53_timer0: timer-cl0-cpu0 {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 55 compatible = "arm,armv8-timer";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 56 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 57 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 58 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 59 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 60 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 61
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 62 pmu: pmu {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 63 compatible = "arm,cortex-a53-pmu";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 64 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 65 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 66
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 67 cbass_main: bus@f0000 {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 68 compatible = "simple-bus";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 69 ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 70 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First Peripheral Window */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 71 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000400>, /* Timesync Router */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 72 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 73 <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 74 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x1a001400>, /* Second Peripheral Window */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 75 <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 76 <0x00 0x30200000 0x00 0x30200000 0x00 0x0000b000>, /* DSS */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 77 <0x00 0x30270000 0x00 0x30270000 0x00 0x00390000>, /* DSI Wrapper */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 78 <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 79 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core Window */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 80 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core Window */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 81 <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 82 <0x00 0x45810000 0x00 0x45810000 0x00 0x03170000>, /* DMSS */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 83 <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 84 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS DAT1 */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 85 <0x00 0x70800000 0x00 0x70800000 0x00 0x00018000>, /* OCSRAM */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 86 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 87 <0x04 0x00000000 0x04 0x00000000 0x01 0x00000000>, /* FSS DAT0 */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 88 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS DAT3 */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 89
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 90 /* Wakeup Domain Range */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 91 <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 92 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 93 <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDGCFG */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 94 <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 95 <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 96 <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 97 <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 98 #address-cells = <2>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 99 #size-cells = <2>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 100
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 @101 cbass_wakeup: bus@43000000 {
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 102 compatible = "simple-bus";
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 103 ranges = <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 104 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 105 <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDGCFG */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 106 <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 107 <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 108 <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 109 <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 110 #address-cells = <2>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 111 #size-cells = <2>;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 112 bootph-all;
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 113 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 114 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 115
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 116 #include "k3-am62l-thermal.dtsi"
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 117 };
5c91f2d6b1283d Vignesh Raghavendra 2025-05-07 118
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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2025-05-09 14:55 [PATCH v5 3/3] arm64: dts: ti: k3-am62l: add initial reference board file kernel test robot
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2025-05-08 3:09 [PATCH v5 0/3] arm64: dts: ti: introduce basic support for the AM62L Bryan Brattlof
2025-05-08 3:09 ` [PATCH v5 3/3] arm64: dts: ti: k3-am62l: add initial reference board file Bryan Brattlof
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