From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Fabiano Rosas" <farosas@suse.de>,
"Laurent Vivier" <lvivier@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v2 01/25] hw/misc/aspeed_hace: Remove unused code for better readability
Date: Tue, 13 May 2025 14:28:31 +0800 [thread overview]
Message-ID: <20250513062901.2256865-2-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com>
In the previous design of the hash framework, accumulative hashing was not
supported. To work around this limitation, commit 5cd7d85 introduced an
iov_cache array to store all the hash data from firmware.
Once the ASPEED HACE model collected all the data, it passed the iov_cache to
the hash API to calculate the final digest.
However, with commit e3c0752, the hash framework now supports accumulative
hashing. This allows us to refactor the ASPEED HACE model, removing redundant
logic and simplifying the implementation for better readability and
maintainability.
As a result, the iov_count variable is no longer needed—it was previously used
to track how many cached entries were used for hashing.
To maintain VMSTATE compatibility after removing this field, the VMSTATE_VERSION
is bumped to 2
This cleanup follows significant changes in commit 4c1d0af4a28d, making the
model more readable.
- Deleted "iov_cache" and "iov_count" from "AspeedHACEState".
- Removed "reconstruct_iov" function and related logic.
- Simplified "do_hash_operation" by eliminating redundant checks.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/misc/aspeed_hace.h | 2 --
hw/misc/aspeed_hace.c | 39 ++---------------------------------
2 files changed, 2 insertions(+), 39 deletions(-)
diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h
index 5d4aa19cfe..b69a038d35 100644
--- a/include/hw/misc/aspeed_hace.h
+++ b/include/hw/misc/aspeed_hace.h
@@ -31,10 +31,8 @@ struct AspeedHACEState {
MemoryRegion iomem;
qemu_irq irq;
- struct iovec iov_cache[ASPEED_HACE_MAX_SG];
uint32_t regs[ASPEED_HACE_NR_REGS];
uint32_t total_req_len;
- uint32_t iov_count;
MemoryRegion *dram_mr;
AddressSpace dram_as;
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index f4bff32a00..9263739ea6 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -142,25 +142,6 @@ static bool has_padding(AspeedHACEState *s, struct iovec *iov,
return false;
}
-static int reconstruct_iov(AspeedHACEState *s, struct iovec *iov, int id,
- uint32_t *pad_offset)
-{
- int i, iov_count;
- if (*pad_offset != 0) {
- s->iov_cache[s->iov_count].iov_base = iov[id].iov_base;
- s->iov_cache[s->iov_count].iov_len = *pad_offset;
- ++s->iov_count;
- }
- for (i = 0; i < s->iov_count; i++) {
- iov[i].iov_base = s->iov_cache[i].iov_base;
- iov[i].iov_len = s->iov_cache[i].iov_len;
- }
- iov_count = s->iov_count;
- s->iov_count = 0;
- s->total_req_len = 0;
- return iov_count;
-}
-
static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
bool acc_mode)
{
@@ -242,19 +223,6 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
iov[0].iov_base = haddr;
iov[0].iov_len = len;
i = 1;
-
- if (s->iov_count) {
- /*
- * In aspeed sdk kernel driver, sg_mode is disabled in hash_final().
- * Thus if we received a request with sg_mode disabled, it is
- * required to check whether cache is empty. If no, we should
- * combine cached iov and the current iov.
- */
- s->total_req_len += len;
- if (has_padding(s, iov, len, &total_msg_len, &pad_offset)) {
- i = reconstruct_iov(s, iov, 0, &pad_offset);
- }
- }
}
if (acc_mode) {
@@ -278,7 +246,6 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
qcrypto_hash_free(s->hash_ctx);
s->hash_ctx = NULL;
- s->iov_count = 0;
s->total_req_len = 0;
}
} else if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf,
@@ -437,7 +404,6 @@ static void aspeed_hace_reset(DeviceState *dev)
}
memset(s->regs, 0, sizeof(s->regs));
- s->iov_count = 0;
s->total_req_len = 0;
}
@@ -469,12 +435,11 @@ static const Property aspeed_hace_properties[] = {
static const VMStateDescription vmstate_aspeed_hace = {
.name = TYPE_ASPEED_HACE,
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AspeedHACEState, ASPEED_HACE_NR_REGS),
VMSTATE_UINT32(total_req_len, AspeedHACEState),
- VMSTATE_UINT32(iov_count, AspeedHACEState),
VMSTATE_END_OF_LIST(),
}
};
--
2.43.0
next prev parent reply other threads:[~2025-05-13 6:29 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-13 6:28 [PATCH v2 00/25] Fix incorrect hash results on AST2700 Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via [this message]
2025-05-13 6:28 ` [PATCH v2 02/25] hw/misc/aspeed_hace: Improve readability and consistency in variable naming Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 03/25] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 04/25] hw/misc/aspeed_hace: Refactor hash buffer setup into helper functions for clarity Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 05/25] hw/misc/aspeed_hace: Split hash execution " Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 13:04 ` Cédric Le Goater
2025-05-14 2:37 ` Jamin Lin
2025-05-14 2:48 ` Jamin Lin
2025-05-14 9:35 ` Cédric Le Goater
2025-05-14 9:41 ` Jamin Lin
2025-05-13 6:28 ` [PATCH v2 06/25] hw/misc/aspeed_hace: Introduce 64-bit hash source address helper function Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 07/25] hw/misc/aspeed_hace: Rename R_HASH_DEST to R_HASH_DIGEST and introduce 64-bit hash digest address helper Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 08/25] hw/misc/aspeed_hace: Support accumulative mode for direct access mode Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 09/25] hw/misc/aspeed_hace: Move register size to instance class and dynamically allocate regs Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 10/25] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 11/25] hw/misc/aspeed_hace: Support DMA 64 bits dram address Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 12/25] hw/misc/aspeed_hace: Add trace-events for better debugging Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 13/25] hw/misc/aspeed_hace: Support to dump plaintext and digest " Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 14/25] tests/qtest: Reorder aspeed test list Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 15/25] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 16/25] test/qtest/hace: Specify explicit array sizes for test vectors and hash results Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 17/25] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 18/25] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 19/25] test/qtest/hace: Add SHA-384 tests for AST2600 Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 20/25] test/qtest/hace: Add tests for AST1030 Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 21/25] test/qtest/hace: Update source data and digest data type to 64-bit Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 22/25] test/qtest/hace: Support 64-bit source and digest addresses for AST2700 Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 23/25] test/qtest/hace: Support to test upper 32 bits of digest and source addresses Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 24/25] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses Jamin Lin via
2025-05-13 6:28 ` [PATCH v2 25/25] test/qtest/hace: Add tests for AST2700 Jamin Lin via
2025-05-13 6:28 ` Jamin Lin via
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