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From: Jamin Lin via <qemu-arm@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Fabiano Rosas" <farosas@suse.de>,
	"Laurent Vivier" <lvivier@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v2 08/25] hw/misc/aspeed_hace: Support accumulative mode for direct access mode
Date: Tue, 13 May 2025 14:28:38 +0800	[thread overview]
Message-ID: <20250513062901.2256865-9-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com>

Enable accumulative mode for direct access mode operations. In direct access
mode, only a single source buffer is used, so the "iovec" count is set to 1.
If "acc_mode" is enabled:
1. Accumulate "total_req_len" with the current request length ("plen").
2. Check for padding and determine whether this is the final request.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/misc/aspeed_hace.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index c5ddc1c99a..ef777bb594 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -151,8 +151,11 @@ static uint64_t hash_get_source_addr(AspeedHACEState *s)
     return src_addr;
 }
 
-static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov)
+static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov,
+                                   bool acc_mode, bool *acc_final_request)
 {
+    uint32_t total_msg_len;
+    uint32_t pad_offset;
     uint64_t src;
     void *haddr;
     hwaddr plen;
@@ -171,9 +174,23 @@ static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov)
     }
 
     iov[0].iov_base = haddr;
-    iov[0].iov_len = plen;
     iov_idx = 1;
 
+    if (acc_mode) {
+        s->total_req_len += plen;
+
+        if (has_padding(s, &iov[0], plen, &total_msg_len,
+                        &pad_offset)) {
+            /* Padding being present indicates the final request */
+            *acc_final_request = true;
+            iov[0].iov_len = pad_offset;
+        } else {
+            iov[0].iov_len = plen;
+        }
+    } else {
+        iov[0].iov_len = plen;
+    }
+
     return iov_idx;
 }
 
@@ -345,7 +362,8 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
     if (sg_mode) {
         iov_idx = hash_prepare_sg_iov(s, iov, acc_mode, &acc_final_request);
     } else {
-        iov_idx = hash_prepare_direct_iov(s, iov);
+        iov_idx = hash_prepare_direct_iov(s, iov, acc_mode,
+                                          &acc_final_request);
     }
 
     if (iov_idx <= 0) {
-- 
2.43.0


WARNING: multiple messages have this Message-ID (diff)
From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Fabiano Rosas" <farosas@suse.de>,
	"Laurent Vivier" <lvivier@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v2 08/25] hw/misc/aspeed_hace: Support accumulative mode for direct access mode
Date: Tue, 13 May 2025 14:28:38 +0800	[thread overview]
Message-ID: <20250513062901.2256865-9-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250513062901.2256865-1-jamin_lin@aspeedtech.com>

Enable accumulative mode for direct access mode operations. In direct access
mode, only a single source buffer is used, so the "iovec" count is set to 1.
If "acc_mode" is enabled:
1. Accumulate "total_req_len" with the current request length ("plen").
2. Check for padding and determine whether this is the final request.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/misc/aspeed_hace.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index c5ddc1c99a..ef777bb594 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -151,8 +151,11 @@ static uint64_t hash_get_source_addr(AspeedHACEState *s)
     return src_addr;
 }
 
-static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov)
+static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov,
+                                   bool acc_mode, bool *acc_final_request)
 {
+    uint32_t total_msg_len;
+    uint32_t pad_offset;
     uint64_t src;
     void *haddr;
     hwaddr plen;
@@ -171,9 +174,23 @@ static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov)
     }
 
     iov[0].iov_base = haddr;
-    iov[0].iov_len = plen;
     iov_idx = 1;
 
+    if (acc_mode) {
+        s->total_req_len += plen;
+
+        if (has_padding(s, &iov[0], plen, &total_msg_len,
+                        &pad_offset)) {
+            /* Padding being present indicates the final request */
+            *acc_final_request = true;
+            iov[0].iov_len = pad_offset;
+        } else {
+            iov[0].iov_len = plen;
+        }
+    } else {
+        iov[0].iov_len = plen;
+    }
+
     return iov_idx;
 }
 
@@ -345,7 +362,8 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
     if (sg_mode) {
         iov_idx = hash_prepare_sg_iov(s, iov, acc_mode, &acc_final_request);
     } else {
-        iov_idx = hash_prepare_direct_iov(s, iov);
+        iov_idx = hash_prepare_direct_iov(s, iov, acc_mode,
+                                          &acc_final_request);
     }
 
     if (iov_idx <= 0) {
-- 
2.43.0



  parent reply	other threads:[~2025-05-13  6:31 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-13  6:28 [PATCH v2 00/25] Fix incorrect hash results on AST2700 Jamin Lin via
2025-05-13  6:28 ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 01/25] hw/misc/aspeed_hace: Remove unused code for better readability Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 02/25] hw/misc/aspeed_hace: Improve readability and consistency in variable naming Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 03/25] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 04/25] hw/misc/aspeed_hace: Refactor hash buffer setup into helper functions for clarity Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 05/25] hw/misc/aspeed_hace: Split hash execution " Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13 13:04   ` Cédric Le Goater
2025-05-14  2:37     ` Jamin Lin
2025-05-14  2:48       ` Jamin Lin
2025-05-14  9:35         ` Cédric Le Goater
2025-05-14  9:41           ` Jamin Lin
2025-05-13  6:28 ` [PATCH v2 06/25] hw/misc/aspeed_hace: Introduce 64-bit hash source address helper function Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 07/25] hw/misc/aspeed_hace: Rename R_HASH_DEST to R_HASH_DIGEST and introduce 64-bit hash digest address helper Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` Jamin Lin via [this message]
2025-05-13  6:28   ` [PATCH v2 08/25] hw/misc/aspeed_hace: Support accumulative mode for direct access mode Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 09/25] hw/misc/aspeed_hace: Move register size to instance class and dynamically allocate regs Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 10/25] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 11/25] hw/misc/aspeed_hace: Support DMA 64 bits dram address Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 12/25] hw/misc/aspeed_hace: Add trace-events for better debugging Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 13/25] hw/misc/aspeed_hace: Support to dump plaintext and digest " Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 14/25] tests/qtest: Reorder aspeed test list Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 15/25] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 16/25] test/qtest/hace: Specify explicit array sizes for test vectors and hash results Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 17/25] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 18/25] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 19/25] test/qtest/hace: Add SHA-384 tests for AST2600 Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 20/25] test/qtest/hace: Add tests for AST1030 Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 21/25] test/qtest/hace: Update source data and digest data type to 64-bit Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 22/25] test/qtest/hace: Support 64-bit source and digest addresses for AST2700 Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 23/25] test/qtest/hace: Support to test upper 32 bits of digest and source addresses Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 24/25] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses Jamin Lin via
2025-05-13  6:28 ` [PATCH v2 25/25] test/qtest/hace: Add tests for AST2700 Jamin Lin via
2025-05-13  6:28   ` Jamin Lin via

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