* Re: [PATCH 2/2] WIP: arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
@ 2025-05-13 6:09 kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2025-05-13 6:09 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
::::::
BCC: lkp@intel.com
CC: llvm@lists.linux.dev
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250505121627.3944728-3-sirius.wang@mediatek.com>
References: <20250505121627.3944728-3-sirius.wang@mediatek.com>
TO: Sirius Wang <sirius.wang@mediatek.com>
TO: Rob Herring <robh@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Conor Dooley <conor+dt@kernel.org>
TO: Matthias Brugger <matthias.bgg@gmail.com>
TO: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
TO: Sean Wang <sean.wang@mediatek.com>
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-mediatek@lists.infradead.org
CC: wenst@chromium.org
CC: Sirius Wang <sirius.wang@mediatek.com>
Hi Sirius,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.15-rc6 next-20250512]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sirius-Wang/WIP-dt-bindings-arm-Add-compatible-for-MediaTek-MT8189/20250505-201837
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20250505121627.3944728-3-sirius.wang%40mediatek.com
patch subject: [PATCH 2/2] WIP: arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
:::::: branch date: 8 days ago
:::::: commit date: 8 days ago
config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20250513/202505131410.57t7Q8aR-lkp@intel.com/config)
compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250513/202505131410.57t7Q8aR-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202505131410.57t7Q8aR-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> arch/arm64/boot/dts/mediatek/mt8189.dtsi:391.17-394.4: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
vim +391 arch/arm64/boot/dts/mediatek/mt8189.dtsi
aeefc838ee5e5a Sirius Wang 2025-05-05 10
aeefc838ee5e5a Sirius Wang 2025-05-05 11 / {
aeefc838ee5e5a Sirius Wang 2025-05-05 12 compatible = "mediatek,mt8189";
aeefc838ee5e5a Sirius Wang 2025-05-05 13 interrupt-parent = <&gic>;
aeefc838ee5e5a Sirius Wang 2025-05-05 14 #address-cells = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 15 #size-cells = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 16
aeefc838ee5e5a Sirius Wang 2025-05-05 17 aliases {
aeefc838ee5e5a Sirius Wang 2025-05-05 18 serial0 = &uart0;
aeefc838ee5e5a Sirius Wang 2025-05-05 19 };
aeefc838ee5e5a Sirius Wang 2025-05-05 20
aeefc838ee5e5a Sirius Wang 2025-05-05 21 cpus {
aeefc838ee5e5a Sirius Wang 2025-05-05 22 #address-cells = <1>;
aeefc838ee5e5a Sirius Wang 2025-05-05 23 #size-cells = <0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 24
aeefc838ee5e5a Sirius Wang 2025-05-05 25 cpu0: cpu@0 {
aeefc838ee5e5a Sirius Wang 2025-05-05 26 device_type = "cpu";
aeefc838ee5e5a Sirius Wang 2025-05-05 27 compatible = "arm,cortex-a55";
aeefc838ee5e5a Sirius Wang 2025-05-05 28 reg = <0x000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 29 enable-method = "psci";
aeefc838ee5e5a Sirius Wang 2025-05-05 30 clock-frequency = <2000000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 31 capacity-dmips-mhz = <742>;
aeefc838ee5e5a Sirius Wang 2025-05-05 32 cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
aeefc838ee5e5a Sirius Wang 2025-05-05 33 i-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 34 i-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 35 i-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 36 d-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 37 d-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 38 d-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 39 next-level-cache = <&l2_0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 40 performance-domains = <&performance 0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 41 #cooling-cells = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 42 };
aeefc838ee5e5a Sirius Wang 2025-05-05 43
aeefc838ee5e5a Sirius Wang 2025-05-05 44 cpu1: cpu@100 {
aeefc838ee5e5a Sirius Wang 2025-05-05 45 device_type = "cpu";
aeefc838ee5e5a Sirius Wang 2025-05-05 46 compatible = "arm,cortex-a55";
aeefc838ee5e5a Sirius Wang 2025-05-05 47 reg = <0x100>;
aeefc838ee5e5a Sirius Wang 2025-05-05 48 enable-method = "psci";
aeefc838ee5e5a Sirius Wang 2025-05-05 49 clock-frequency = <2000000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 50 capacity-dmips-mhz = <742>;
aeefc838ee5e5a Sirius Wang 2025-05-05 51 cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
aeefc838ee5e5a Sirius Wang 2025-05-05 52 i-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 53 i-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 54 i-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 55 d-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 56 d-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 57 d-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 58 next-level-cache = <&l2_0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 59 performance-domains = <&performance 0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 60 #cooling-cells = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 61 };
aeefc838ee5e5a Sirius Wang 2025-05-05 62
aeefc838ee5e5a Sirius Wang 2025-05-05 63 cpu2: cpu@200 {
aeefc838ee5e5a Sirius Wang 2025-05-05 64 device_type = "cpu";
aeefc838ee5e5a Sirius Wang 2025-05-05 65 compatible = "arm,cortex-a55";
aeefc838ee5e5a Sirius Wang 2025-05-05 66 reg = <0x200>;
aeefc838ee5e5a Sirius Wang 2025-05-05 67 enable-method = "psci";
aeefc838ee5e5a Sirius Wang 2025-05-05 68 clock-frequency = <2000000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 69 capacity-dmips-mhz = <742>;
aeefc838ee5e5a Sirius Wang 2025-05-05 70 cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
aeefc838ee5e5a Sirius Wang 2025-05-05 71 i-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 72 i-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 73 i-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 74 d-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 75 d-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 76 d-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 77 next-level-cache = <&l2_0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 78 performance-domains = <&performance 0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 79 #cooling-cells = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 80 };
aeefc838ee5e5a Sirius Wang 2025-05-05 81
aeefc838ee5e5a Sirius Wang 2025-05-05 82 cpu3: cpu@300 {
aeefc838ee5e5a Sirius Wang 2025-05-05 83 device_type = "cpu";
aeefc838ee5e5a Sirius Wang 2025-05-05 84 compatible = "arm,cortex-a55";
aeefc838ee5e5a Sirius Wang 2025-05-05 85 reg = <0x300>;
aeefc838ee5e5a Sirius Wang 2025-05-05 86 enable-method = "psci";
aeefc838ee5e5a Sirius Wang 2025-05-05 87 clock-frequency = <2000000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 88 capacity-dmips-mhz = <742>;
aeefc838ee5e5a Sirius Wang 2025-05-05 89 cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
aeefc838ee5e5a Sirius Wang 2025-05-05 90 i-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 91 i-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 92 i-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 93 d-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 94 d-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 95 d-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 96 next-level-cache = <&l2_0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 97 performance-domains = <&performance 0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 98 #cooling-cells = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 99 };
aeefc838ee5e5a Sirius Wang 2025-05-05 100
aeefc838ee5e5a Sirius Wang 2025-05-05 101 cpu4: cpu@400 {
aeefc838ee5e5a Sirius Wang 2025-05-05 102 device_type = "cpu";
aeefc838ee5e5a Sirius Wang 2025-05-05 103 compatible = "arm,cortex-a55";
aeefc838ee5e5a Sirius Wang 2025-05-05 104 reg = <0x400>;
aeefc838ee5e5a Sirius Wang 2025-05-05 105 enable-method = "psci";
aeefc838ee5e5a Sirius Wang 2025-05-05 106 clock-frequency = <2000000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 107 capacity-dmips-mhz = <742>;
aeefc838ee5e5a Sirius Wang 2025-05-05 108 cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
aeefc838ee5e5a Sirius Wang 2025-05-05 109 i-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 110 i-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 111 i-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 112 d-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 113 d-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 114 d-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 115 next-level-cache = <&l2_0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 116 performance-domains = <&performance 0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 117 #cooling-cells = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 118 };
aeefc838ee5e5a Sirius Wang 2025-05-05 119
aeefc838ee5e5a Sirius Wang 2025-05-05 120 cpu5: cpu@500 {
aeefc838ee5e5a Sirius Wang 2025-05-05 121 device_type = "cpu";
aeefc838ee5e5a Sirius Wang 2025-05-05 122 compatible = "arm,cortex-a55";
aeefc838ee5e5a Sirius Wang 2025-05-05 123 reg = <0x500>;
aeefc838ee5e5a Sirius Wang 2025-05-05 124 enable-method = "psci";
aeefc838ee5e5a Sirius Wang 2025-05-05 125 clock-frequency = <2000000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 126 capacity-dmips-mhz = <742>;
aeefc838ee5e5a Sirius Wang 2025-05-05 127 cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
aeefc838ee5e5a Sirius Wang 2025-05-05 128 i-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 129 i-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 130 i-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 131 d-cache-size = <32768>;
aeefc838ee5e5a Sirius Wang 2025-05-05 132 d-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 133 d-cache-sets = <128>;
aeefc838ee5e5a Sirius Wang 2025-05-05 134 next-level-cache = <&l2_0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 135 performance-domains = <&performance 0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 136 #cooling-cells = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 137 };
aeefc838ee5e5a Sirius Wang 2025-05-05 138
aeefc838ee5e5a Sirius Wang 2025-05-05 139 cpu6: cpu@600 {
aeefc838ee5e5a Sirius Wang 2025-05-05 140 device_type = "cpu";
aeefc838ee5e5a Sirius Wang 2025-05-05 141 compatible = "arm,cortex-a78";
aeefc838ee5e5a Sirius Wang 2025-05-05 142 reg = <0x600>;
aeefc838ee5e5a Sirius Wang 2025-05-05 143 enable-method = "psci";
aeefc838ee5e5a Sirius Wang 2025-05-05 144 clock-frequency = <3000000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 145 capacity-dmips-mhz = <958>;
aeefc838ee5e5a Sirius Wang 2025-05-05 146 cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_vcore &s2idle>;
aeefc838ee5e5a Sirius Wang 2025-05-05 147 i-cache-size = <65536>;
aeefc838ee5e5a Sirius Wang 2025-05-05 148 i-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 149 i-cache-sets = <256>;
aeefc838ee5e5a Sirius Wang 2025-05-05 150 d-cache-size = <65536>;
aeefc838ee5e5a Sirius Wang 2025-05-05 151 d-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 152 d-cache-sets = <256>;
aeefc838ee5e5a Sirius Wang 2025-05-05 153 next-level-cache = <&l2_1>;
aeefc838ee5e5a Sirius Wang 2025-05-05 154 performance-domains = <&performance 1>;
aeefc838ee5e5a Sirius Wang 2025-05-05 155 #cooling-cells = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 156 };
aeefc838ee5e5a Sirius Wang 2025-05-05 157
aeefc838ee5e5a Sirius Wang 2025-05-05 158 cpu7: cpu@700 {
aeefc838ee5e5a Sirius Wang 2025-05-05 159 device_type = "cpu";
aeefc838ee5e5a Sirius Wang 2025-05-05 160 compatible = "arm,cortex-a78";
aeefc838ee5e5a Sirius Wang 2025-05-05 161 reg = <0x700>;
aeefc838ee5e5a Sirius Wang 2025-05-05 162 enable-method = "psci";
aeefc838ee5e5a Sirius Wang 2025-05-05 163 clock-frequency = <3000000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 164 capacity-dmips-mhz = <958>;
aeefc838ee5e5a Sirius Wang 2025-05-05 165 cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_vcore &s2idle>;
aeefc838ee5e5a Sirius Wang 2025-05-05 166 i-cache-size = <65536>;
aeefc838ee5e5a Sirius Wang 2025-05-05 167 i-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 168 i-cache-sets = <256>;
aeefc838ee5e5a Sirius Wang 2025-05-05 169 d-cache-size = <65536>;
aeefc838ee5e5a Sirius Wang 2025-05-05 170 d-cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 171 d-cache-sets = <256>;
aeefc838ee5e5a Sirius Wang 2025-05-05 172 next-level-cache = <&l2_1>;
aeefc838ee5e5a Sirius Wang 2025-05-05 173 performance-domains = <&performance 1>;
aeefc838ee5e5a Sirius Wang 2025-05-05 174 #cooling-cells = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 175 };
aeefc838ee5e5a Sirius Wang 2025-05-05 176
aeefc838ee5e5a Sirius Wang 2025-05-05 177 cpu-map {
aeefc838ee5e5a Sirius Wang 2025-05-05 178 cluster0 {
aeefc838ee5e5a Sirius Wang 2025-05-05 179 core0 {
aeefc838ee5e5a Sirius Wang 2025-05-05 180 cpu = <&cpu0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 181 };
aeefc838ee5e5a Sirius Wang 2025-05-05 182 core1 {
aeefc838ee5e5a Sirius Wang 2025-05-05 183 cpu = <&cpu1>;
aeefc838ee5e5a Sirius Wang 2025-05-05 184 };
aeefc838ee5e5a Sirius Wang 2025-05-05 185 core2 {
aeefc838ee5e5a Sirius Wang 2025-05-05 186 cpu = <&cpu2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 187 };
aeefc838ee5e5a Sirius Wang 2025-05-05 188 core3 {
aeefc838ee5e5a Sirius Wang 2025-05-05 189 cpu = <&cpu3>;
aeefc838ee5e5a Sirius Wang 2025-05-05 190 };
aeefc838ee5e5a Sirius Wang 2025-05-05 191 core4 {
aeefc838ee5e5a Sirius Wang 2025-05-05 192 cpu = <&cpu4>;
aeefc838ee5e5a Sirius Wang 2025-05-05 193 };
aeefc838ee5e5a Sirius Wang 2025-05-05 194 core5 {
aeefc838ee5e5a Sirius Wang 2025-05-05 195 cpu = <&cpu5>;
aeefc838ee5e5a Sirius Wang 2025-05-05 196 };
aeefc838ee5e5a Sirius Wang 2025-05-05 197 };
aeefc838ee5e5a Sirius Wang 2025-05-05 198
aeefc838ee5e5a Sirius Wang 2025-05-05 199 cluster1 {
aeefc838ee5e5a Sirius Wang 2025-05-05 200 core0 {
aeefc838ee5e5a Sirius Wang 2025-05-05 201 cpu = <&cpu6>;
aeefc838ee5e5a Sirius Wang 2025-05-05 202 };
aeefc838ee5e5a Sirius Wang 2025-05-05 203 core1 {
aeefc838ee5e5a Sirius Wang 2025-05-05 204 cpu = <&cpu7>;
aeefc838ee5e5a Sirius Wang 2025-05-05 205 };
aeefc838ee5e5a Sirius Wang 2025-05-05 206 };
aeefc838ee5e5a Sirius Wang 2025-05-05 207 };
aeefc838ee5e5a Sirius Wang 2025-05-05 208
aeefc838ee5e5a Sirius Wang 2025-05-05 209 idle-states {
aeefc838ee5e5a Sirius Wang 2025-05-05 210 entry-method = "arm,psci";
aeefc838ee5e5a Sirius Wang 2025-05-05 211
aeefc838ee5e5a Sirius Wang 2025-05-05 212 cpuoff_l: cpuoff-l {
aeefc838ee5e5a Sirius Wang 2025-05-05 213 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 214 arm,psci-suspend-param = <0x00010000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 215 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 216 entry-latency-us = <97>;
aeefc838ee5e5a Sirius Wang 2025-05-05 217 exit-latency-us = <252>;
aeefc838ee5e5a Sirius Wang 2025-05-05 218 min-residency-us = <6710>;
aeefc838ee5e5a Sirius Wang 2025-05-05 219 };
aeefc838ee5e5a Sirius Wang 2025-05-05 220
aeefc838ee5e5a Sirius Wang 2025-05-05 221 cpuoff_m: cpuoff-m {
aeefc838ee5e5a Sirius Wang 2025-05-05 222 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 223 arm,psci-suspend-param = <0x00010000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 224 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 225 entry-latency-us = <53>;
aeefc838ee5e5a Sirius Wang 2025-05-05 226 exit-latency-us = <143>;
aeefc838ee5e5a Sirius Wang 2025-05-05 227 min-residency-us = <2120>;
aeefc838ee5e5a Sirius Wang 2025-05-05 228 };
aeefc838ee5e5a Sirius Wang 2025-05-05 229
aeefc838ee5e5a Sirius Wang 2025-05-05 230 cpuoff_b: cpuoff-b {
aeefc838ee5e5a Sirius Wang 2025-05-05 231 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 232 arm,psci-suspend-param = <0x00010000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 233 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 234 entry-latency-us = <40>;
aeefc838ee5e5a Sirius Wang 2025-05-05 235 exit-latency-us = <107>;
aeefc838ee5e5a Sirius Wang 2025-05-05 236 min-residency-us = <2580>;
aeefc838ee5e5a Sirius Wang 2025-05-05 237 };
aeefc838ee5e5a Sirius Wang 2025-05-05 238
aeefc838ee5e5a Sirius Wang 2025-05-05 239 clusteroff_l: clusteroff-l {
aeefc838ee5e5a Sirius Wang 2025-05-05 240 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 241 arm,psci-suspend-param = <0x01010001>;
aeefc838ee5e5a Sirius Wang 2025-05-05 242 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 243 entry-latency-us = <109>;
aeefc838ee5e5a Sirius Wang 2025-05-05 244 exit-latency-us = <325>;
aeefc838ee5e5a Sirius Wang 2025-05-05 245 min-residency-us = <6710>;
aeefc838ee5e5a Sirius Wang 2025-05-05 246 };
aeefc838ee5e5a Sirius Wang 2025-05-05 247
aeefc838ee5e5a Sirius Wang 2025-05-05 248 clusteroff_m: clusteroff-m {
aeefc838ee5e5a Sirius Wang 2025-05-05 249 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 250 arm,psci-suspend-param = <0x01010001>;
aeefc838ee5e5a Sirius Wang 2025-05-05 251 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 252 entry-latency-us = <59>;
aeefc838ee5e5a Sirius Wang 2025-05-05 253 exit-latency-us = <188>;
aeefc838ee5e5a Sirius Wang 2025-05-05 254 min-residency-us = <2120>;
aeefc838ee5e5a Sirius Wang 2025-05-05 255 };
aeefc838ee5e5a Sirius Wang 2025-05-05 256
aeefc838ee5e5a Sirius Wang 2025-05-05 257 clusteroff_b: clusteroff-b {
aeefc838ee5e5a Sirius Wang 2025-05-05 258 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 259 arm,psci-suspend-param = <0x01010001>;
aeefc838ee5e5a Sirius Wang 2025-05-05 260 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 261 entry-latency-us = <43>;
aeefc838ee5e5a Sirius Wang 2025-05-05 262 exit-latency-us = <138>;
aeefc838ee5e5a Sirius Wang 2025-05-05 263 min-residency-us = <2580>;
aeefc838ee5e5a Sirius Wang 2025-05-05 264 };
aeefc838ee5e5a Sirius Wang 2025-05-05 265
aeefc838ee5e5a Sirius Wang 2025-05-05 266 mcusysoff_l: mcusysoff-l {
aeefc838ee5e5a Sirius Wang 2025-05-05 267 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 268 arm,psci-suspend-param = <0x02010007>;
aeefc838ee5e5a Sirius Wang 2025-05-05 269 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 270 entry-latency-us = <1357>;
aeefc838ee5e5a Sirius Wang 2025-05-05 271 exit-latency-us = <835>;
aeefc838ee5e5a Sirius Wang 2025-05-05 272 min-residency-us = <6710>;
aeefc838ee5e5a Sirius Wang 2025-05-05 273 };
aeefc838ee5e5a Sirius Wang 2025-05-05 274
aeefc838ee5e5a Sirius Wang 2025-05-05 275 mcusysoff_m: mcusysoff-m {
aeefc838ee5e5a Sirius Wang 2025-05-05 276 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 277 arm,psci-suspend-param = <0x02010007>;
aeefc838ee5e5a Sirius Wang 2025-05-05 278 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 279 entry-latency-us = <1202>;
aeefc838ee5e5a Sirius Wang 2025-05-05 280 exit-latency-us = <679>;
aeefc838ee5e5a Sirius Wang 2025-05-05 281 min-residency-us = <2120>;
aeefc838ee5e5a Sirius Wang 2025-05-05 282 };
aeefc838ee5e5a Sirius Wang 2025-05-05 283
aeefc838ee5e5a Sirius Wang 2025-05-05 284 mcusysoff_b: mcusysoff-b {
aeefc838ee5e5a Sirius Wang 2025-05-05 285 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 286 arm,psci-suspend-param = <0x02010007>;
aeefc838ee5e5a Sirius Wang 2025-05-05 287 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 288 entry-latency-us = <1143>;
aeefc838ee5e5a Sirius Wang 2025-05-05 289 exit-latency-us = <611>;
aeefc838ee5e5a Sirius Wang 2025-05-05 290 min-residency-us = <2580>;
aeefc838ee5e5a Sirius Wang 2025-05-05 291 };
aeefc838ee5e5a Sirius Wang 2025-05-05 292
aeefc838ee5e5a Sirius Wang 2025-05-05 293 system_vcore: system-vcore {
aeefc838ee5e5a Sirius Wang 2025-05-05 294 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 295 arm,psci-suspend-param = <0x020100ff>;
aeefc838ee5e5a Sirius Wang 2025-05-05 296 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 297 entry-latency-us = <940>;
aeefc838ee5e5a Sirius Wang 2025-05-05 298 exit-latency-us = <3500>;
aeefc838ee5e5a Sirius Wang 2025-05-05 299 min-residency-us = <35200>;
aeefc838ee5e5a Sirius Wang 2025-05-05 300 };
aeefc838ee5e5a Sirius Wang 2025-05-05 301
aeefc838ee5e5a Sirius Wang 2025-05-05 302 s2idle: s2idle {
aeefc838ee5e5a Sirius Wang 2025-05-05 303 compatible = "arm,idle-state";
aeefc838ee5e5a Sirius Wang 2025-05-05 304 arm,psci-suspend-param = <0x020180ff>;
aeefc838ee5e5a Sirius Wang 2025-05-05 305 local-timer-stop;
aeefc838ee5e5a Sirius Wang 2025-05-05 306 entry-latency-us = <10000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 307 exit-latency-us = <10000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 308 min-residency-us = <4294967295>;
aeefc838ee5e5a Sirius Wang 2025-05-05 309 };
aeefc838ee5e5a Sirius Wang 2025-05-05 310 };
aeefc838ee5e5a Sirius Wang 2025-05-05 311
aeefc838ee5e5a Sirius Wang 2025-05-05 312 l2_0: l2-cache0 {
aeefc838ee5e5a Sirius Wang 2025-05-05 313 compatible = "cache";
aeefc838ee5e5a Sirius Wang 2025-05-05 314 cache-level = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 315 cache-size = <131072>;
aeefc838ee5e5a Sirius Wang 2025-05-05 316 cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 317 cache-sets = <512>;
aeefc838ee5e5a Sirius Wang 2025-05-05 318 next-level-cache = <&l3_0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 319 cache-unified;
aeefc838ee5e5a Sirius Wang 2025-05-05 320 };
aeefc838ee5e5a Sirius Wang 2025-05-05 321
aeefc838ee5e5a Sirius Wang 2025-05-05 322 l2_1: l2-cache1 {
aeefc838ee5e5a Sirius Wang 2025-05-05 323 compatible = "cache";
aeefc838ee5e5a Sirius Wang 2025-05-05 324 cache-level = <2>;
aeefc838ee5e5a Sirius Wang 2025-05-05 325 cache-size = <262144>;
aeefc838ee5e5a Sirius Wang 2025-05-05 326 cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 327 cache-sets = <512>;
aeefc838ee5e5a Sirius Wang 2025-05-05 328 next-level-cache = <&l3_0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 329 cache-unified;
aeefc838ee5e5a Sirius Wang 2025-05-05 330 };
aeefc838ee5e5a Sirius Wang 2025-05-05 331
aeefc838ee5e5a Sirius Wang 2025-05-05 332 l3_0: l3-cache {
aeefc838ee5e5a Sirius Wang 2025-05-05 333 compatible = "cache";
aeefc838ee5e5a Sirius Wang 2025-05-05 334 cache-level = <3>;
aeefc838ee5e5a Sirius Wang 2025-05-05 335 cache-size = <1048576>;
aeefc838ee5e5a Sirius Wang 2025-05-05 336 cache-line-size = <64>;
aeefc838ee5e5a Sirius Wang 2025-05-05 337 cache-sets = <2048>;
aeefc838ee5e5a Sirius Wang 2025-05-05 338 cache-unified;
aeefc838ee5e5a Sirius Wang 2025-05-05 339 };
aeefc838ee5e5a Sirius Wang 2025-05-05 340 };
aeefc838ee5e5a Sirius Wang 2025-05-05 341
aeefc838ee5e5a Sirius Wang 2025-05-05 342 psci {
aeefc838ee5e5a Sirius Wang 2025-05-05 343 compatible = "arm,psci-1.0";
aeefc838ee5e5a Sirius Wang 2025-05-05 344 method = "smc";
aeefc838ee5e5a Sirius Wang 2025-05-05 345 };
aeefc838ee5e5a Sirius Wang 2025-05-05 346
aeefc838ee5e5a Sirius Wang 2025-05-05 347 clocks {
aeefc838ee5e5a Sirius Wang 2025-05-05 348 clk_null: clk-null {
aeefc838ee5e5a Sirius Wang 2025-05-05 349 compatible = "fixed-clock";
aeefc838ee5e5a Sirius Wang 2025-05-05 350 #clock-cells = <0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 351 clock-frequency = <0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 352 };
aeefc838ee5e5a Sirius Wang 2025-05-05 353
aeefc838ee5e5a Sirius Wang 2025-05-05 354 clk32k: clk32k {
aeefc838ee5e5a Sirius Wang 2025-05-05 355 compatible = "fixed-clock";
aeefc838ee5e5a Sirius Wang 2025-05-05 356 #clock-cells = <0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 357 clock-frequency = <32000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 358 };
aeefc838ee5e5a Sirius Wang 2025-05-05 359
aeefc838ee5e5a Sirius Wang 2025-05-05 360 clk26m: clk26m {
aeefc838ee5e5a Sirius Wang 2025-05-05 361 compatible = "fixed-clock";
aeefc838ee5e5a Sirius Wang 2025-05-05 362 #clock-cells = <0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 363 clock-frequency = <26000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 364 };
aeefc838ee5e5a Sirius Wang 2025-05-05 365
aeefc838ee5e5a Sirius Wang 2025-05-05 366 clk13m: clk13m {
aeefc838ee5e5a Sirius Wang 2025-05-05 367 compatible = "fixed-clock";
aeefc838ee5e5a Sirius Wang 2025-05-05 368 #clock-cells = <0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 369 clock-frequency = <13000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 370 };
aeefc838ee5e5a Sirius Wang 2025-05-05 371
aeefc838ee5e5a Sirius Wang 2025-05-05 372 ulposc: ulposc {
aeefc838ee5e5a Sirius Wang 2025-05-05 373 compatible = "fixed-clock";
aeefc838ee5e5a Sirius Wang 2025-05-05 374 #clock-cells = <0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 375 clock-frequency = <520000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 376 };
aeefc838ee5e5a Sirius Wang 2025-05-05 377
aeefc838ee5e5a Sirius Wang 2025-05-05 378 ulposc3: ulposc3 {
aeefc838ee5e5a Sirius Wang 2025-05-05 379 compatible = "fixed-clock";
aeefc838ee5e5a Sirius Wang 2025-05-05 380 #clock-cells = <0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 381 clock-frequency = <26000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 382 };
aeefc838ee5e5a Sirius Wang 2025-05-05 383
aeefc838ee5e5a Sirius Wang 2025-05-05 384 clk104m: clk104m {
aeefc838ee5e5a Sirius Wang 2025-05-05 385 compatible = "fixed-clock";
aeefc838ee5e5a Sirius Wang 2025-05-05 386 #clock-cells = <0>;
aeefc838ee5e5a Sirius Wang 2025-05-05 387 clock-frequency = <104000000>;
aeefc838ee5e5a Sirius Wang 2025-05-05 388 };
aeefc838ee5e5a Sirius Wang 2025-05-05 389 };
aeefc838ee5e5a Sirius Wang 2025-05-05 390
aeefc838ee5e5a Sirius Wang 2025-05-05 @391 memory: memory {
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 2+ messages in thread* [PATCH 0/2] Add mt8189 dts evaluation board and Mafefile
@ 2025-05-05 12:15 Sirius Wang
2025-05-05 12:15 ` [PATCH 2/2] WIP: arm64: dts: mt8189: " Sirius Wang
0 siblings, 1 reply; 2+ messages in thread
From: Sirius Wang @ 2025-05-05 12:15 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sean Wang
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, wenst,
Sirius Wang
MT8189 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55
and 2 CA78 cores. MT8189 share many HW IP with MT8188 series.
We add basic chip support for MediaTek MT8189 on evaluation board.
In this series, we also add dt-bindings document definition for MT8189.
Sirius Wang (2):
WIP: dt-bindings: arm: Add compatible for MediaTek MT8189
WIP: arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
.../devicetree/bindings/arm/mediatek.yaml | 4 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 +
arch/arm64/boot/dts/mediatek/mt8189.dtsi | 441 ++++++++++++++++++
4 files changed, 466 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
--
2.45.2
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH 2/2] WIP: arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
2025-05-05 12:15 [PATCH 0/2] " Sirius Wang
@ 2025-05-05 12:15 ` Sirius Wang
0 siblings, 0 replies; 2+ messages in thread
From: Sirius Wang @ 2025-05-05 12:15 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sean Wang
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, wenst,
Sirius Wang
MT8189 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55
and 2 CA78 cores. MT8189 share many HW IP with MT8188 series.
We add basic chip support for MediaTek MT8189 on evaluation board.
BUG=b:387230785
TEST=emerge-skywalker chromeos-kernel-6_6
Signed-off-by: Sirius Wang <sirius.wang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 +
arch/arm64/boot/dts/mediatek/mt8189.dtsi | 441 ++++++++++++++++++++
3 files changed, 462 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 3aa06476c6c0..ad2ac9e1bb79 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
new file mode 100644
index 000000000000..e5d9ce1b8e61
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Sirius Wang <sirius.wang@mediatek.com>
+ */
+/dts-v1/;
+#include "mt8189.dtsi"
+
+/ {
+ model = "MediaTek MT8189 evaluation board";
+ compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
+
+ chosen: chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
new file mode 100644
index 000000000000..de59d858bcf3
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
@@ -0,0 +1,441 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+ compatible = "mediatek,mt8189";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x400>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x500>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ clock-frequency = <3000000000>;
+ capacity-dmips-mhz = <958>;
+ cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_vcore &s2idle>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ clock-frequency = <3000000000>;
+ capacity-dmips-mhz = <958>;
+ cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_vcore &s2idle>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ core4 {
+ cpu = <&cpu4>;
+ };
+ core5 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ cpuoff_l: cpuoff-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <97>;
+ exit-latency-us = <252>;
+ min-residency-us = <6710>;
+ };
+
+ cpuoff_m: cpuoff-m {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <53>;
+ exit-latency-us = <143>;
+ min-residency-us = <2120>;
+ };
+
+ cpuoff_b: cpuoff-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <40>;
+ exit-latency-us = <107>;
+ min-residency-us = <2580>;
+ };
+
+ clusteroff_l: clusteroff-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <109>;
+ exit-latency-us = <325>;
+ min-residency-us = <6710>;
+ };
+
+ clusteroff_m: clusteroff-m {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <59>;
+ exit-latency-us = <188>;
+ min-residency-us = <2120>;
+ };
+
+ clusteroff_b: clusteroff-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <43>;
+ exit-latency-us = <138>;
+ min-residency-us = <2580>;
+ };
+
+ mcusysoff_l: mcusysoff-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x02010007>;
+ local-timer-stop;
+ entry-latency-us = <1357>;
+ exit-latency-us = <835>;
+ min-residency-us = <6710>;
+ };
+
+ mcusysoff_m: mcusysoff-m {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x02010007>;
+ local-timer-stop;
+ entry-latency-us = <1202>;
+ exit-latency-us = <679>;
+ min-residency-us = <2120>;
+ };
+
+ mcusysoff_b: mcusysoff-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x02010007>;
+ local-timer-stop;
+ entry-latency-us = <1143>;
+ exit-latency-us = <611>;
+ min-residency-us = <2580>;
+ };
+
+ system_vcore: system-vcore {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x020100ff>;
+ local-timer-stop;
+ entry-latency-us = <940>;
+ exit-latency-us = <3500>;
+ min-residency-us = <35200>;
+ };
+
+ s2idle: s2idle {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x020180ff>;
+ local-timer-stop;
+ entry-latency-us = <10000>;
+ exit-latency-us = <10000>;
+ min-residency-us = <4294967295>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ clocks {
+ clk_null: clk-null {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ clk32k: clk32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+
+ clk26m: clk26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk13m: clk13m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13000000>;
+ };
+
+ ulposc: ulposc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <520000000>;
+ };
+
+ ulposc3: ulposc3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk104m: clk104m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <104000000>;
+ };
+ };
+
+ memory: memory {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0xC0000000>;
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-frequency = <13000000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0xc000000 0 0x40000>, /* distributor */
+ <0 0xc040000 0 0x200000>; /* redistributor */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ uart0: serial@11001000 {
+ compatible = "mediatek,mt6577-uart";
+ reg = <0 0x11001000 0 0x1000>;
+ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>;
+ clock-names = "baud", "bus";
+ uart-line = <0>;
+ };
+ };
+};
--
2.45.2
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2025-05-13 6:09 [PATCH 2/2] WIP: arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile kernel test robot
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2025-05-05 12:15 [PATCH 0/2] " Sirius Wang
2025-05-05 12:15 ` [PATCH 2/2] WIP: arm64: dts: mt8189: " Sirius Wang
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