From: Conor Dooley <conor@kernel.org>
To: soc@kernel.org
Cc: conor@kernel.org, linux-riscv@lists.infradead.org
Subject: [GIT PULL 2/3] RISC-V cache drivers for v6.16
Date: Fri, 16 May 2025 11:40:07 +0100 [thread overview]
Message-ID: <20250516-liability-facility-667fc14a2a85@spud> (raw)
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Hey Arnd,
Please pull some cache driver/binding updates for 6.16.
Thanks,
Conor.
The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:
Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-cache-for-v6.16
for you to fetch changes up to 51b081cdb92377d7f923912d589cab414db600c4:
dt-bindings: cache: add QiLai compatible to ax45mp (2025-05-14 16:53:02 +0100)
----------------------------------------------------------------
RISC-V cache drivers for v6.16
SiFive:
Add support for the Eswin EIC7700 SoC, which needs to make sure of the
non-standard cache-ops provided by the ccache driver.
Bindings:
Conversions for two Marvell bindings to yaml, and additions of two
soc-specific compatibles to the axm45mp bindings.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
----------------------------------------------------------------
Ben Zong-You Xie (1):
dt-bindings: cache: add QiLai compatible to ax45mp
Conor Dooley (1):
dt-bindings: cache: add specific RZ/Five compatible to ax45mp
Pinkesh Vaghela (1):
cache: sifive_ccache: Add ESWIN EIC7700 support
Pritesh Patel (1):
dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility
Rob Herring (Arm) (2):
dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
dt-bindings: cache: Convert marvell,tauros2-cache to DT schema
.../bindings/cache/andestech,ax45mp-cache.yaml | 20 +++++++++-
.../bindings/cache/marvell,feroceon-cache.txt | 16 --------
.../bindings/cache/marvell,kirkwood-cache.yaml | 45 ++++++++++++++++++++++
.../bindings/cache/marvell,tauros2-cache.txt | 17 --------
.../bindings/cache/marvell,tauros2-cache.yaml | 39 +++++++++++++++++++
.../devicetree/bindings/cache/sifive,ccache0.yaml | 44 +++++++++++++++++++--
drivers/cache/sifive_ccache.c | 2 +
7 files changed, 146 insertions(+), 37 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt
create mode 100644 Documentation/devicetree/bindings/cache/marvell,kirkwood-cache.yaml
delete mode 100644 Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt
create mode 100644 Documentation/devicetree/bindings/cache/marvell,tauros2-cache.yaml
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: soc@kernel.org
Cc: conor@kernel.org, linux-riscv@lists.infradead.org
Subject: [GIT PULL 2/3] RISC-V cache drivers for v6.16
Date: Fri, 16 May 2025 11:40:07 +0100 [thread overview]
Message-ID: <20250516-liability-facility-667fc14a2a85@spud> (raw)
[-- Attachment #1: Type: text/plain, Size: 2388 bytes --]
Hey Arnd,
Please pull some cache driver/binding updates for 6.16.
Thanks,
Conor.
The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:
Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-cache-for-v6.16
for you to fetch changes up to 51b081cdb92377d7f923912d589cab414db600c4:
dt-bindings: cache: add QiLai compatible to ax45mp (2025-05-14 16:53:02 +0100)
----------------------------------------------------------------
RISC-V cache drivers for v6.16
SiFive:
Add support for the Eswin EIC7700 SoC, which needs to make sure of the
non-standard cache-ops provided by the ccache driver.
Bindings:
Conversions for two Marvell bindings to yaml, and additions of two
soc-specific compatibles to the axm45mp bindings.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
----------------------------------------------------------------
Ben Zong-You Xie (1):
dt-bindings: cache: add QiLai compatible to ax45mp
Conor Dooley (1):
dt-bindings: cache: add specific RZ/Five compatible to ax45mp
Pinkesh Vaghela (1):
cache: sifive_ccache: Add ESWIN EIC7700 support
Pritesh Patel (1):
dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility
Rob Herring (Arm) (2):
dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
dt-bindings: cache: Convert marvell,tauros2-cache to DT schema
.../bindings/cache/andestech,ax45mp-cache.yaml | 20 +++++++++-
.../bindings/cache/marvell,feroceon-cache.txt | 16 --------
.../bindings/cache/marvell,kirkwood-cache.yaml | 45 ++++++++++++++++++++++
.../bindings/cache/marvell,tauros2-cache.txt | 17 --------
.../bindings/cache/marvell,tauros2-cache.yaml | 39 +++++++++++++++++++
.../devicetree/bindings/cache/sifive,ccache0.yaml | 44 +++++++++++++++++++--
drivers/cache/sifive_ccache.c | 2 +
7 files changed, 146 insertions(+), 37 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt
create mode 100644 Documentation/devicetree/bindings/cache/marvell,kirkwood-cache.yaml
delete mode 100644 Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt
create mode 100644 Documentation/devicetree/bindings/cache/marvell,tauros2-cache.yaml
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next reply other threads:[~2025-05-16 10:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-16 10:40 Conor Dooley [this message]
2025-05-16 10:40 ` [GIT PULL 2/3] RISC-V cache drivers for v6.16 Conor Dooley
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