From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org
Cc: dave@stgolabs.net, jonathan.cameron@huawei.com,
alison.schofield@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, dan.j.williams@intel.com,
Gregory Price <gourry@gourry.net>, Li Ming <ming.li@zohomail.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: [PATCH v3 1/9] cxl/region: Add decoder check to check_commit_order()
Date: Wed, 21 May 2025 11:34:35 -0700 [thread overview]
Message-ID: <20250521183443.3828320-2-dave.jiang@intel.com> (raw)
In-Reply-To: <20250521183443.3828320-1-dave.jiang@intel.com>
check_commit_order() attempts to convert a device to a decoder without
making sure the device is a decoder. So far this has been working due
to pure luck. Issue discovered while doing deferred dport probing when
child ports are now in the midst of decoders due to ordering change
of child port additions. Add a check before attempting to do decoder
conversion.
Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/region.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index c3f4dc244df7..a91d4eb061e4 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -788,7 +788,12 @@ static size_t show_targetN(struct cxl_region *cxlr, char *buf, int pos)
static int check_commit_order(struct device *dev, void *data)
{
- struct cxl_decoder *cxld = to_cxl_decoder(dev);
+ struct cxl_decoder *cxld;
+
+ if (!is_switch_decoder(dev))
+ return 0;
+
+ cxld = to_cxl_decoder(dev);
/*
* if port->commit_end is not the only free decoder, then out of
--
2.49.0
next prev parent reply other threads:[~2025-05-21 18:34 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-21 18:34 [PATCH v3 0/9] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-05-21 18:34 ` Dave Jiang [this message]
2025-05-21 18:34 ` [PATCH v3 2/9] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-05-21 18:39 ` Dave Jiang
2025-05-22 9:18 ` Jonathan Cameron
2025-05-22 9:43 ` Li Ming
2025-05-21 18:34 ` [PATCH v3 3/9] cxl: Separate out CXL dport->id vs actual dport hardware id Dave Jiang
2025-05-22 9:43 ` Li Ming
2025-05-28 12:53 ` Robert Richter
2025-05-21 18:34 ` [PATCH v3 4/9] cxl: Remove adding of port_num via devm_cxl_add_dport() Dave Jiang
2025-05-21 18:34 ` [PATCH v3 5/9] cxl: Defer hardware dport->port_id assignment and registers probing Dave Jiang
2025-05-22 10:55 ` Li Ming
2025-06-04 15:27 ` Robert Richter
2025-05-21 18:34 ` [PATCH v3 6/9] cxl/test: Add workaround for cxl_test for cxl_core calling mocked functions Dave Jiang
2025-05-21 18:34 ` [PATCH v3 7/9] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-05-22 11:04 ` Li Ming
2025-05-21 18:34 ` [PATCH v3 8/9] cxl: Create an xarray to tie a host bridge to the cxl_root Dave Jiang
2025-05-21 18:34 ` [PATCH v3 9/9] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-05-30 13:51 ` [PATCH v3 0/9] cxl: Delay HB port and switch dport probing until endpoint dev probe Robert Richter
2025-06-03 13:55 ` Dave Jiang
2025-06-04 15:44 ` Robert Richter
2025-06-05 15:17 ` Dave Jiang
2025-06-06 9:44 ` Robert Richter
2025-06-13 15:15 ` Gregory Price
2025-06-13 15:43 ` Dave Jiang
2025-06-17 17:47 ` Robert Richter
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