Re: [PATCH v3 2/9] cxl: Add helper to detect top of CXL device topology

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Wed, 21 May 2025 11:39:29 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> On 5/21/25 11:34 AM, Dave Jiang wrote:
> > Add a helper to replace the open code detection of CXL device hierarchy
> > root. The helper will be used for delayed hostbridge port creation later
> > on.
> > 
> > Reviewed-by: Jonathan Cameron <Jonsathan.Cameron@huawei.com>  
> 
> I'll fix the email address. :)

One day I'll grow up and learn to spell my own name ;)
Thanks!

J
(playing is safe :)

> DJ
> 
> > Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> > ---
> >  drivers/cxl/core/port.c | 15 ++++++++++-----
> >  1 file changed, 10 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> > index 726bd4a7de27..cafb1b13cba1 100644
> > --- a/drivers/cxl/core/port.c
> > +++ b/drivers/cxl/core/port.c
> > @@ -39,6 +39,15 @@ DECLARE_RWSEM(cxl_region_rwsem);
> >  static DEFINE_IDA(cxl_port_ida);
> >  static DEFINE_XARRAY(cxl_root_buses);
> >  
> > +/*
> > + * The terminal device in PCI is NULL and @platform_bus
> > + * for platform devices (for cxl_test)
> > + */
> > +static bool is_cxl_hierarchy_head(struct device *dev)
> > +{
> > +	return (!dev || dev == &platform_bus);
> > +}
> > +
> >  int cxl_num_decoders_committed(struct cxl_port *port)
> >  {
> >  	lockdep_assert_held(&cxl_region_rwsem);
> > @@ -1642,11 +1651,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
> >  		struct device *uport_dev;
> >  		struct cxl_dport *dport;
> >  
> > -		/*
> > -		 * The terminal "grandparent" in PCI is NULL and @platform_bus
> > -		 * for platform devices
> > -		 */
> > -		if (!dport_dev || dport_dev == &platform_bus)
> > +		if (is_cxl_hierarchy_head(dport_dev))
> >  			return 0;
> >  
> >  		uport_dev = dport_dev->parent;  
> 
> 
>