* [PATCH v2 1/2] dt-bindings: clk: fixed-mmio-clock: Add optional ready reg
2025-05-28 14:09 [PATCH v2 0/2] clk: fixed-mmio: Add optional ready registers Edgar E. Iglesias
@ 2025-05-28 14:09 ` Edgar E. Iglesias
2025-05-28 14:19 ` Rob Herring
2025-05-28 14:09 ` [PATCH v2 2/2] clk: fixed-mmio: Add optional poll for clk readiness Edgar E. Iglesias
1 sibling, 1 reply; 4+ messages in thread
From: Edgar E. Iglesias @ 2025-05-28 14:09 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, jank
Cc: edgar.iglesias, linux-clk, devicetree, linux-kernel
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
Add an optional ready register and properties describing bitfields
that signal when the clock is ready. This can for example be useful
to describe PLL lock bits.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
---
.../bindings/clock/fixed-mmio-clock.yaml | 37 ++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml
index e22fc272d023..57419b4de343 100644
--- a/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml
@@ -10,6 +10,11 @@ description:
This binding describes a fixed-rate clock for which the frequency can
be read from a single 32-bit memory mapped I/O register.
+ An optional ready register can be specified in a second reg entry.
+ The ready register will be polled until it signals ready prior to reading
+ the fixed rate. This is useful for example to optionally wait for a PLL
+ to lock.
+
It was designed for test systems, like FPGA, not for complete,
finished SoCs.
@@ -21,7 +26,10 @@ properties:
const: fixed-mmio-clock
reg:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: Fixed rate register
+ - description: Optional clock ready register
"#clock-cells":
const: 0
@@ -29,6 +37,24 @@ properties:
clock-output-names:
maxItems: 1
+ ready-timeout-us:
+ description:
+ Optional timeout in micro-seconds when polling for clock readiness.
+ 0 means no timeout.
+ default: 0
+
+ ready-mask:
+ description:
+ Optional mask to apply when reading the ready register.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0xffffffff
+
+ ready-value:
+ description:
+ When a ready register is specified in reg, poll the ready reg until
+ ready-reg & ready-mask == ready-value.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
required:
- compatible
- reg
@@ -44,4 +70,13 @@ examples:
reg = <0xfd020004 0x4>;
clock-output-names = "sysclk";
};
+ - |
+ clock@fd040000 {
+ compatible = "fixed-mmio-clock";
+ #clock-cells = <0>;
+ reg = <0xfd040000 0x4 0xfd040004 0x4>;
+ ready-mask = <1>;
+ ready-value = <1>;
+ clock-output-names = "pclk";
+ };
...
--
2.43.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v2 2/2] clk: fixed-mmio: Add optional poll for clk readiness
2025-05-28 14:09 [PATCH v2 0/2] clk: fixed-mmio: Add optional ready registers Edgar E. Iglesias
2025-05-28 14:09 ` [PATCH v2 1/2] dt-bindings: clk: fixed-mmio-clock: Add optional ready reg Edgar E. Iglesias
@ 2025-05-28 14:09 ` Edgar E. Iglesias
1 sibling, 0 replies; 4+ messages in thread
From: Edgar E. Iglesias @ 2025-05-28 14:09 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, jank
Cc: edgar.iglesias, linux-clk, devicetree, linux-kernel
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
Add optional poll for clk readiness prior to reading the fixed rate.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
---
drivers/clk/clk-fixed-mmio.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/clk-fixed-mmio.c b/drivers/clk/clk-fixed-mmio.c
index 3bfcf4cd98a2..1b764c446ce5 100644
--- a/drivers/clk/clk-fixed-mmio.c
+++ b/drivers/clk/clk-fixed-mmio.c
@@ -11,10 +11,36 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
+static int fixed_mmio_clk_wait_ready(struct device_node *node,
+ void __iomem *base)
+{
+ u32 ready_mask;
+ u32 ready_val;
+ u32 timeout;
+ u32 v;
+
+ if (of_property_read_u32(node, "ready-timeout-us", &timeout))
+ timeout = 0;
+
+ if (of_property_read_u32(node, "ready-mask", &ready_mask))
+ ready_mask = ~0;
+
+ if (of_property_read_u32(node, "ready-val", &ready_val)) {
+ pr_err("%pOFn: missing ready-val property\n", node);
+ return -EINVAL;
+ }
+
+ pr_info("%pOFn: wait for clock\n", node);
+ return readl_relaxed_poll_timeout_atomic(base, v,
+ (v & ready_mask) == ready_val,
+ 1, timeout);
+}
+
static struct clk_hw *fixed_mmio_clk_setup(struct device_node *node)
{
struct clk_hw *clk;
@@ -23,6 +49,15 @@ static struct clk_hw *fixed_mmio_clk_setup(struct device_node *node)
u32 freq;
int ret;
+ base = of_iomap(node, 1);
+ if (base) {
+ /* Wait for clk to get ready. */
+ ret = fixed_mmio_clk_wait_ready(node, base);
+ iounmap(base);
+ if (ret)
+ return ERR_PTR(ret);
+ }
+
base = of_iomap(node, 0);
if (!base) {
pr_err("%pOFn: failed to map address\n", node);
--
2.43.0
^ permalink raw reply related [flat|nested] 4+ messages in thread