From: Jesse Taube <jesse@rivosinc.com>
To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org
Cc: "Atish Patra" <atishp@atishpatra.org>,
"Anup Patel" <anup@brainfault.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Himanshu Chauhan" <hchauhan@ventanamicro.com>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Jesse Taube" <jesse@rivosinc.com>,
"Andrew Jones" <andrew.jones@linux.dev>
Subject: [kvm-unit-tests PATCH v3 1/2] riscv: Add RV_INSN_LEN to processor.h
Date: Thu, 5 Jun 2025 09:18:05 -0700 [thread overview]
Message-ID: <20250605161806.1206850-1-jesse@rivosinc.com> (raw)
When handeling traps and faults it is offten necessary to know the size
of the instruction at epc. Add RV_INSN_LEN to calculate the
instruction size.
Signed-off-by: Jesse Taube <jesse@rivosinc.com>
---
lib/riscv/asm/processor.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h
index 40104272..631ce226 100644
--- a/lib/riscv/asm/processor.h
+++ b/lib/riscv/asm/processor.h
@@ -7,6 +7,8 @@
#define EXCEPTION_CAUSE_MAX 24
#define INTERRUPT_CAUSE_MAX 16
+#define RV_INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4)
+
typedef void (*exception_fn)(struct pt_regs *);
struct thread_info {
--
2.43.0
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jesse Taube <jesse@rivosinc.com>
To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org
Cc: "Atish Patra" <atishp@atishpatra.org>,
"Anup Patel" <anup@brainfault.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Himanshu Chauhan" <hchauhan@ventanamicro.com>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Jesse Taube" <jesse@rivosinc.com>,
"Andrew Jones" <andrew.jones@linux.dev>
Subject: [kvm-unit-tests PATCH v3 1/2] riscv: Add RV_INSN_LEN to processor.h
Date: Thu, 5 Jun 2025 09:18:05 -0700 [thread overview]
Message-ID: <20250605161806.1206850-1-jesse@rivosinc.com> (raw)
When handeling traps and faults it is offten necessary to know the size
of the instruction at epc. Add RV_INSN_LEN to calculate the
instruction size.
Signed-off-by: Jesse Taube <jesse@rivosinc.com>
---
lib/riscv/asm/processor.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h
index 40104272..631ce226 100644
--- a/lib/riscv/asm/processor.h
+++ b/lib/riscv/asm/processor.h
@@ -7,6 +7,8 @@
#define EXCEPTION_CAUSE_MAX 24
#define INTERRUPT_CAUSE_MAX 16
+#define RV_INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4)
+
typedef void (*exception_fn)(struct pt_regs *);
struct thread_info {
--
2.43.0
next reply other threads:[~2025-06-05 16:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-05 16:18 Jesse Taube [this message]
2025-06-05 16:18 ` [kvm-unit-tests PATCH v3 1/2] riscv: Add RV_INSN_LEN to processor.h Jesse Taube
2025-06-05 16:18 ` [kvm-unit-tests PATCH v3 2/2] riscv: sbi: Add SBI Debug Triggers Extension tests Jesse Taube
2025-06-05 16:18 ` Jesse Taube
2025-06-06 8:48 ` Andrew Jones
2025-06-06 8:48 ` Andrew Jones
2025-06-06 8:32 ` [kvm-unit-tests PATCH v3 1/2] riscv: Add RV_INSN_LEN to processor.h Andrew Jones
2025-06-06 8:32 ` Andrew Jones
2025-07-02 14:49 ` Andrew Jones
2025-07-02 14:49 ` Andrew Jones
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