[PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

From: E Shattow <e@freeshell.de>
To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: E Shattow <e@freeshell.de>
Subject: [PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110
Date: Fri,  6 Jun 2025 06:02:35 -0700	[thread overview]
Message-ID: <20250606130253.1105273-1-e@freeshell.de> (raw)

Bring in additional downstream U-Boot boot loader changes for StarFive
VisionFive2 board target (and related JH7110 common boards). There is a
memory controller with no downstream dt-binding; create a basic dt-binding
(and not any Linux driver) in support of the memory-controller dts node
needed by U-Boot starfive_ddr.c driver. Also add bootph-pre-ram hinting
to jh7110.dtsi needed at SPL boot phase.

Changes since RFC:

- Drop additional timer node from series as not strictly needed for boot.
- Add patch for starfive,jh7110-dmc binding
- Adjust ordering of bootph-pre-ram hints to follow devicetree style guide

E Shattow (3):
  dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
  riscv: dts: starfive: jh7110: add memory controller node
  riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
    loader

 .../starfive,jh7110-dmc.yaml                  | 76 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 22 ++++++
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

base-commit: d50108706a63dfd896db42172bf9f6aebec219c5
-- 
2.49.0

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