[PATCH v1 0/7] Hex value prefix case cleanup

[PATCH v1 0/7] Hex value prefix case cleanup

[E Shattow]

Make consistent use of lowercase hexadecimal prefix '0x' throughout U-Boot.

There are a few remaining uses of uppercase 'X' to denote hexadecimal prefix
or placeholder in documentation and error messages.

External devicetree-rebasing dts/upstream and the generated code of
xilinx/zynq are ignored for the series.

E Shattow (7):
  configs: use lowercase hex prefix style
  board: use lowercase hex prefix style
  drivers: use lowercase hex prefix style
  tools: use lowercase hex prefix style
  lib: use lowercase hex prefix style
  arch: use lowercase hex prefix style
  include: use lowercase hex prefix style

 arch/arm/dts/fsl-imx8qxp-ai_ml.dts            | 16 +++---
 arch/arm/dts/hi3660.dtsi                      |  2 +-
 arch/arm/dts/imx7-colibri.dtsi                |  2 +-
 .../asm/arch-fsl-layerscape/immap_lsch3.h     |  2 +-
 arch/arm/include/asm/arch-mx6/mx6sl_pins.h    |  8 +--
 arch/arm/include/asm/arch-rockchip/cru_px30.h |  6 +--
 .../arm/include/asm/arch-rockchip/f_rockusb.h |  2 +-
 .../include/asm/arch-rockchip/sdram_px30.h    |  2 +-
 .../include/asm/arch-rockchip/sdram_rk3328.h  |  2 +-
 .../include/asm/arch-rockchip/sdram_rv1126.h  |  2 +-
 arch/arm/include/asm/iproc-common/sysmap.h    | 20 ++++----
 arch/arm/mach-at91/include/mach/at91_wdt.h    |  2 +-
 arch/arm/mach-exynos/include/mach/dsim.h      |  2 +-
 arch/arm/mach-imx/iomux-v3.c                  |  2 +-
 .../mach-keystone/include/mach/hardware-k2g.h |  4 +-
 arch/arm/mach-kirkwood/include/mach/mpp.h     |  2 +-
 arch/arm/mach-omap2/lowlevel_init.S           |  2 +-
 arch/arm/mach-sc5xx/init/dmcinit.c            |  2 +-
 .../include/mach/clock_manager_s10.h          |  6 +--
 arch/arm/mach-uniphier/bcu/bcu-ld4.c          |  2 +-
 arch/arm/mach-zynqmp/include/mach/hardware.h  |  2 +-
 arch/mips/mach-jz47xx/jz4780/pll.c            |  2 +-
 arch/powerpc/include/asm/immap_85xx.h         |  6 +--
 arch/powerpc/include/asm/processor.h          |  4 +-
 board/freescale/common/qixis.h                |  4 +-
 board/gateworks/gw_ventana/gw_ventana_spl.c   | 28 +++++------
 board/kontron/sl-mx6ul/spl.c                  |  2 +-
 configs/am62x_evm_r5_ethboot_defconfig        |  2 +-
 configs/starfive_visionfive2_defconfig        |  2 +-
 drivers/ata/dwc_ahsata_priv.h                 |  4 +-
 drivers/clk/renesas/r8a774a1-cpg-mssr.c       |  2 +-
 drivers/clk/stm32/clk-stm32mp1.c              |  2 +-
 drivers/ddr/altera/iossm_mailbox.c            |  2 +-
 drivers/mmc/sdhci-cadence6.c                  |  2 +-
 drivers/mmc/zynq_sdhci.c                      |  2 +-
 drivers/mtd/nand/raw/lpc32xx_nand_mlc.c       |  4 +-
 drivers/net/fsl-mc/mc.c                       |  2 +-
 drivers/net/phy/ca_phy.c                      |  2 +-
 drivers/phy/rockchip/phy-rockchip-typec.c     |  2 +-
 drivers/power/regulator/act8846.c             |  4 +-
 drivers/ram/k3-ddrss/k3-ddrss.c               |  2 +-
 drivers/ram/octeon/octeon3_lmc.c              |  2 +-
 drivers/sound/max98088.h                      | 50 +++++++++----------
 drivers/sound/max98095.h                      |  2 +-
 drivers/video/bridge/dp501.c                  |  2 +-
 drivers/video/hx8238d.c                       |  2 +-
 drivers/video/zynqmp/zynqmp_dpsub.h           |  2 +-
 include/fsl_esdhc.h                           |  2 +-
 include/fsl_esdhc_imx.h                       |  2 +-
 include/mc13892.h                             |  2 +-
 .../external/mbedtls/library/ecp_curves_new.c | 46 ++++++++---------
 tools/Kconfig                                 |  2 +-
 52 files changed, 142 insertions(+), 142 deletions(-)


base-commit: b3f69c14187d413610abbc2b82d1a3752cb342c1
-- 
2.49.0

[PATCH v1 1/7] configs: use lowercase hex prefix style

[E Shattow]

Use consistent lowercase hex prefix style in configs/*

Signed-off-by: E Shattow <e@freeshell.de>
---
 configs/am62x_evm_r5_ethboot_defconfig | 2 +-
 configs/starfive_visionfive2_defconfig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/am62x_evm_r5_ethboot_defconfig b/configs/am62x_evm_r5_ethboot_defconfig
index 0d823743907..96b2c28825f 100644
--- a/configs/am62x_evm_r5_ethboot_defconfig
+++ b/configs/am62x_evm_r5_ethboot_defconfig
@@ -9,7 +9,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_MMC=n
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
-CONFIG_SPL_BSS_MAX_SIZE=0X3100
+CONFIG_SPL_BSS_MAX_SIZE=0x3100
 CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_ETH=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index e145ced8db8..fd5bd6efa06 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -98,7 +98,7 @@ CONFIG_SYS_I2C_DW=y
 CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SPL_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0X50
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_SPL_MMC_HS400_SUPPORT=y
 CONFIG_MMC_DW=y
-- 
2.49.0

[PATCH v1 2/7] board: use lowercase hex prefix style

[E Shattow]

Use consistent lowercase hex prefix style in board/*

Does not change auto-generated files in xilinx/zynq/*/ps7_init_gpl.c

Signed-off-by: E Shattow <e@freeshell.de>
---
 board/freescale/common/qixis.h              |  4 +--
 board/gateworks/gw_ventana/gw_ventana_spl.c | 28 ++++++++++-----------
 board/kontron/sl-mx6ul/spl.c                |  2 +-
 3 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 784046ac4e0..0a0df6f34f8 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -136,8 +136,8 @@ void qixis_write_i2c(unsigned int reg, u8 value);
 
 #define QIXIS_SDCLKIN		0x08
 #define QIXIS_SDCLKOUT		0x02
-#define QIXIS_DAT5_6_7		0X02
-#define QIXIS_DAT4		0X01
+#define QIXIS_DAT5_6_7		0x02
+#define QIXIS_DAT4		0x01
 
 #define QIXIS_EVDD_BY_SDHC_VS	0x0c
 
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index 3de4727b2ed..4385732a617 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -366,34 +366,34 @@ static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
 
 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
 	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0X00480047,
-	.p0_mpwldectrl1 = 0X003D003F,
+	.p0_mpwldectrl0 = 0x00480047,
+	.p0_mpwldectrl1 = 0x003D003F,
 	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0X423E0241,
-	.p0_mpdgctrl1 = 0X022B022C,
+	.p0_mpdgctrl0 = 0x423E0241,
+	.p0_mpdgctrl1 = 0x022B022C,
 	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0X49454A4A,
+	.p0_mprddlctl = 0x49454A4A,
 	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0X2E372C32,
+	.p0_mpwrdlctl = 0x2E372C32,
 };
 
 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
 	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0X00220021,
-	.p0_mpwldectrl1 = 0X00200030,
-	.p1_mpwldectrl0 = 0X002D0027,
-	.p1_mpwldectrl1 = 0X00150026,
+	.p0_mpwldectrl0 = 0x00220021,
+	.p0_mpwldectrl1 = 0x00200030,
+	.p1_mpwldectrl0 = 0x002D0027,
+	.p1_mpwldectrl1 = 0x00150026,
 	/* Read DQS Gating calibration */
 	.p0_mpdgctrl0 = 0x43330342,
 	.p0_mpdgctrl1 = 0x0339034A,
 	.p1_mpdgctrl0 = 0x032F0325,
 	.p1_mpdgctrl1 = 0x032F022E,
 	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0X3A2E3437,
-	.p1_mprddlctl = 0X35312F3F,
+	.p0_mprddlctl = 0x3A2E3437,
+	.p1_mprddlctl = 0x35312F3F,
 	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0X33363B37,
-	.p1_mpwrdlctl = 0X40304239,
+	.p0_mpwrdlctl = 0x33363B37,
+	.p1_mpwrdlctl = 0x40304239,
 };
 
 static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c
index b1758858705..33e5337bcbc 100644
--- a/board/kontron/sl-mx6ul/spl.c
+++ b/board/kontron/sl-mx6ul/spl.c
@@ -204,7 +204,7 @@ static struct mx6_ddr3_cfg mem_512M_ddr = {
 
 static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = {
 	.p0_mpwldectrl0 = 0x00000000,
-	.p0_mpdgctrl0 = 0X01440144,
+	.p0_mpdgctrl0 = 0x01440144,
 	.p0_mprddlctl = 0x40405454,
 	.p0_mpwrdlctl = 0x40404E4C,
 };
-- 
2.49.0

[PATCH v1 3/7] drivers: use lowercase hex prefix style

[E Shattow]

Use consistent lowercase hex prefix style in drivers/*

Does not change hex prefix case in allcaps uppercase style error messages

Signed-off-by: E Shattow <e@freeshell.de>
---
 drivers/ata/dwc_ahsata_priv.h             |  4 +-
 drivers/clk/renesas/r8a774a1-cpg-mssr.c   |  2 +-
 drivers/clk/stm32/clk-stm32mp1.c          |  2 +-
 drivers/ddr/altera/iossm_mailbox.c        |  2 +-
 drivers/mmc/sdhci-cadence6.c              |  2 +-
 drivers/mmc/zynq_sdhci.c                  |  2 +-
 drivers/mtd/nand/raw/lpc32xx_nand_mlc.c   |  4 +-
 drivers/net/fsl-mc/mc.c                   |  2 +-
 drivers/net/phy/ca_phy.c                  |  2 +-
 drivers/phy/rockchip/phy-rockchip-typec.c |  2 +-
 drivers/power/regulator/act8846.c         |  4 +-
 drivers/ram/k3-ddrss/k3-ddrss.c           |  2 +-
 drivers/ram/octeon/octeon3_lmc.c          |  2 +-
 drivers/sound/max98088.h                  | 50 +++++++++++------------
 drivers/sound/max98095.h                  |  2 +-
 drivers/video/bridge/dp501.c              |  2 +-
 drivers/video/hx8238d.c                   |  2 +-
 drivers/video/zynqmp/zynqmp_dpsub.h       |  2 +-
 18 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/drivers/ata/dwc_ahsata_priv.h b/drivers/ata/dwc_ahsata_priv.h
index 0c2cd5446b5..f2a118420f9 100644
--- a/drivers/ata/dwc_ahsata_priv.h
+++ b/drivers/ata/dwc_ahsata_priv.h
@@ -117,8 +117,8 @@
 #define SATA_HOST_GPARAM1R_PHY_TYPE	0x00001000
 #define SATA_HOST_GPARAM1R_RETURN_ERR	0x00000400
 #define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK	0x00000300
-#define SATA_HOST_GPARAM1R_S_HADDR	0X00000080
-#define SATA_HOST_GPARAM1R_M_HADDR	0X00000040
+#define SATA_HOST_GPARAM1R_S_HADDR	0x00000080
+#define SATA_HOST_GPARAM1R_M_HADDR	0x00000040
 
 /* Global Parameter 2 Register */
 #define SATA_HOST_GPARAM2R_DEV_CP	0x00004000
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index d23041a8026..c8972106d90 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -305,7 +305,7 @@ static const struct mstp_stop_table r8a774a1_mstp_table[] = {
 	{ 0xD00C7C1F, 0, 0xD00C7C1F, 0 },
 	{ 0x80000004, 0, 0x80000004, 0 },
 	{ 0x00DF0006, 0, 0x00DF0006, 0 },
-	{ 0XC5EACCCE, 0, 0XC5EACCCE, 0 },
+	{ 0xC5EACCCE, 0, 0xC5EACCCE, 0 },
 	{ 0x29E1401C, 0, 0x29E1401C, 0 },
 	{ 0x00009FF1, 0, 0x00009FF1, 0 },
 	{ 0xFC4FDFE0, 0, 0xFC4FDFE0, 0 },
diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
index 9cb69a01f7f..823ce132d0b 100644
--- a/drivers/clk/stm32/clk-stm32mp1.c
+++ b/drivers/clk/stm32/clk-stm32mp1.c
@@ -117,7 +117,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define RCC_DSICKSELR		0x924
 #define RCC_ADCCKSELR		0x928
 #define RCC_MP_APB1ENSETR	0xA00
-#define RCC_MP_APB2ENSETR	0XA08
+#define RCC_MP_APB2ENSETR	0xA08
 #define RCC_MP_APB3ENSETR	0xA10
 #define RCC_MP_AHB2ENSETR	0xA18
 #define RCC_MP_AHB3ENSETR	0xA20
diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c
index fc09dde3f9e..21f94959a04 100644
--- a/drivers/ddr/altera/iossm_mailbox.c
+++ b/drivers/ddr/altera/iossm_mailbox.c
@@ -41,7 +41,7 @@
 
 /* Offset of Mailbox Read-only Registers  */
 #define IOSSM_MAILBOX_HEADER_OFFSET			0x0
-#define IOSSM_MEM_INTF_INFO_0_OFFSET			0X200
+#define IOSSM_MEM_INTF_INFO_0_OFFSET			0x200
 #define IOSSM_MEM_INTF_INFO_1_OFFSET			0x280
 #define IOSSM_MEM_TECHNOLOGY_INTF0_OFFSET		0x210
 #define IOSSM_MEM_TECHNOLOGY_INTF1_OFFSET		0x290
diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c
index a5ed87321ab..9a92b8437a6 100644
--- a/drivers/mmc/sdhci-cadence6.c
+++ b/drivers/mmc/sdhci-cadence6.c
@@ -19,7 +19,7 @@
 #include "sdhci-cadence.h"
 
 /* IO Delay Information */
-#define SDHCI_CDNS_HRS07		0X1C
+#define SDHCI_CDNS_HRS07		0x1C
 #define   SDHCI_CDNS_HRS07_RW_COMPENSATE	GENMASK(20, 16)
 #define   SDHCI_CDNS_HRS07_IDELAY_VAL		GENMASK(4, 0)
 
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 0e2bdab4e7e..2375b15539b 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -83,7 +83,7 @@
 
 #define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN	39
 #define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL		146
-#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL		0X77
+#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL		0x77
 
 struct arasan_sdhci_clk_data {
 	int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
index 4430c4e93ee..7779e63fa5d 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
@@ -165,9 +165,9 @@ static void lpc32xx_cmd_ctrl(struct mtd_info *mtd, int cmd,
 		return;
 
 	if (ctrl & NAND_CLE)
-		writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->cmd);
+		writeb(cmd & 0xff, &lpc32xx_nand_mlc_registers->cmd);
 	else if (ctrl & NAND_ALE)
-		writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->addr);
+		writeb(cmd & 0xff, &lpc32xx_nand_mlc_registers->addr);
 }
 
 /**
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index c2869ce4010..86daf0fb2bb 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -45,7 +45,7 @@
 #define MC_BUFFER_SIZE   (1024 * 1024 * 16)
 #define MAGIC_MC 0x4d430100
 #define MC_FW_ADDR_MASK_LOW 0xE0000000
-#define MC_FW_ADDR_MASK_HIGH 0X1FFFF
+#define MC_FW_ADDR_MASK_HIGH 0x1FFFF
 #define MC_STRUCT_BUFFER_OFFSET 0x01000000
 #define MC_OFFSET_DELTA MC_STRUCT_BUFFER_OFFSET
 
diff --git a/drivers/net/phy/ca_phy.c b/drivers/net/phy/ca_phy.c
index 5b2c67d2fda..72d370274a1 100644
--- a/drivers/net/phy/ca_phy.c
+++ b/drivers/net/phy/ca_phy.c
@@ -73,7 +73,7 @@ static void __external_phy_init(struct phy_device *phydev, int reset_phy)
 	val &= ~(1 << 2);
 	phy_write(phydev, MDIO_DEVAD_NONE, 27, val);
 
-	/* REG31 write 0X0000, back to page0 */
+	/* REG31 write 0x0000, back to page0 */
 	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
 }
 
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
index c7459dbc5fc..c48a5cd5267 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -284,7 +284,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * clock 0: PLL 0 div 1
  * clock 1: PLL 1 div 2
  */
-#define CLK_PLL_CONFIG			0X30
+#define CLK_PLL_CONFIG			0x30
 #define CLK_PLL_MASK			0x33
 
 #define CMN_READY			BIT(0)
diff --git a/drivers/power/regulator/act8846.c b/drivers/power/regulator/act8846.c
index d3e72da0d35..144032692f6 100644
--- a/drivers/power/regulator/act8846.c
+++ b/drivers/power/regulator/act8846.c
@@ -29,7 +29,7 @@ enum {
 	REG_SYS0,
 	REG_SYS1,
 	REG1_VOL	= 0x10,
-	REG1_CTL	= 0X11,
+	REG1_CTL	= 0x11,
 	REG2_VOL0	= 0x20,
 	REG2_VOL1,
 	REG2_CTL,
@@ -41,7 +41,7 @@ enum {
 	REG4_CTL,
 	REG5_VOL	= 0x50,
 	REG5_CTL,
-	REG6_VOL	= 0X58,
+	REG6_VOL	= 0x58,
 	REG6_CTL,
 	REG7_VOL	= 0x60,
 	REG7_CTL,
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index ff87faf6a22..6590d57ad84 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -35,7 +35,7 @@
 
 #define DDRSS_V2A_CTL_REG_SDRAM_IDX_CALC(x)	((ilog2(x) - 16) << 5)
 #define DDRSS_V2A_CTL_REG_SDRAM_IDX_MASK	(~(0x1F << 0x5))
-#define DDRSS_V2A_CTL_REG_REGION_IDX_MASK	(~(0X1F))
+#define DDRSS_V2A_CTL_REG_REGION_IDX_MASK	(~(0x1F))
 #define DDRSS_V2A_CTL_REG_REGION_IDX_DEFAULT	0xF
 
 #define DDRSS_ECC_CTRL_REG_DEFAULT		0x0
diff --git a/drivers/ram/octeon/octeon3_lmc.c b/drivers/ram/octeon/octeon3_lmc.c
index eaef0fa5c12..dc4b8f8cf23 100644
--- a/drivers/ram/octeon/octeon3_lmc.c
+++ b/drivers/ram/octeon/octeon3_lmc.c
@@ -8692,7 +8692,7 @@ int init_octeon3_ddr3_interface(struct ddr_priv *priv,
 		bank_bits = min((int)bank_bits, 4);
 
 		spd_package =
-		    0XFF & read_spd(&dimm_config_table[0], 0,
+		    0xFF & read_spd(&dimm_config_table[0], 0,
 				    DDR4_SPD_PACKAGE_TYPE);
 		if (spd_package & 0x80) {	// non-monolithic device
 			is_stacked_die = ((spd_package & 0x73) == 0x11);
diff --git a/drivers/sound/max98088.h b/drivers/sound/max98088.h
index b1307a73623..2ca6ca1f734 100644
--- a/drivers/sound/max98088.h
+++ b/drivers/sound/max98088.h
@@ -15,14 +15,14 @@
 #define M98088_REG_JACK_STAUS		0x02
 #define M98088_REG_BATTERY_VOLTAGE	0x03
 #define M98088_REG_IRQ_ENABLE		0x0f
-#define M98088_REG_SYS_CLK		0X10
+#define M98088_REG_SYS_CLK		0x10
 #define M98088_REG_DAI1_CLKMODE		0x11
 #define M98088_REG_DAI1_CLKCFG_HI	0x12
 #define M98088_REG_DAI1_CLKCFG_LO	0x13
 #define M98088_REG_DAI1_FORMAT		0x14
 #define M98088_REG_DAI1_CLOCK		0x15
 #define M98088_REG_DAI1_IOCFG		0x16
-#define M98088_REG_DAI1_TDM		0X17
+#define M98088_REG_DAI1_TDM		0x17
 #define M98088_REG_DAI1_FILTERS		0x18
 #define M98088_REG_DAI2_CLKMODE		0x19
 #define M98088_REG_DAI2_CLKCFG_HI	0x1a
@@ -30,10 +30,10 @@
 #define M98088_REG_DAI2_FORMAT		0x1c
 #define M98088_REG_DAI2_CLOCK		0x1d
 #define M98088_REG_DAI2_IOCFG		0x1e
-#define M98088_REG_DAI2_TDM		0X1f
+#define M98088_REG_DAI2_TDM		0x1f
 #define M98088_REG_DAI2_FILTERS		0x20
-#define M98088_REG_SRC			0X21
-#define M98088_REG_MIX_DAC		0X22
+#define M98088_REG_SRC			0x21
+#define M98088_REG_MIX_DAC		0x22
 #define M98088_REG_MIX_ADC_LEFT		0x23
 #define M98088_REG_MIX_ADC_RIGHT	0x24
 #define M98088_REG_MIX_HP_LEFT		0x25
@@ -50,37 +50,37 @@
 #define M98088_REG_LVL_DAI1_PLAY_EQ	0x30
 #define M98088_REG_LVL_DAI2_PLAY	0x31
 #define M98088_REG_LVL_DAI2_PLAY_EQ	0x32
-#define M98088_REG_LVL_ADC_L		0X33
-#define M98088_REG_LVL_ADC_R		0X34
-#define M98088_REG_LVL_MIC1		0X35
-#define M98088_REG_LVL_MIC2		0X36
-#define M98088_REG_LVL_INA		0X37
-#define M98088_REG_LVL_INB		0X38
-#define M98088_REG_LVL_HP_L		0X39
-#define M98088_REG_LVL_HP_R		0X3a
-#define M98088_REG_LVL_REC_L		0X3b
-#define M98088_REG_LVL_REC_R		0X3c
-#define M98088_REG_LVL_SPK_L		0X3d
-#define M98088_REG_LVL_SPK_R		0X3e
+#define M98088_REG_LVL_ADC_L		0x33
+#define M98088_REG_LVL_ADC_R		0x34
+#define M98088_REG_LVL_MIC1		0x35
+#define M98088_REG_LVL_MIC2		0x36
+#define M98088_REG_LVL_INA		0x37
+#define M98088_REG_LVL_INB		0x38
+#define M98088_REG_LVL_HP_L		0x39
+#define M98088_REG_LVL_HP_R		0x3a
+#define M98088_REG_LVL_REC_L		0x3b
+#define M98088_REG_LVL_REC_R		0x3c
+#define M98088_REG_LVL_SPK_L		0x3d
+#define M98088_REG_LVL_SPK_R		0x3e
 #define M98088_REG_MICAGC_CFG		0x3f
 #define M98088_REG_MICAGC_THRESH	0x40
-#define M98088_REG_SPKDHP		0X41
+#define M98088_REG_SPKDHP		0x41
 #define M98088_REG_SPKDHP_THRESH	0x42
 #define M98088_REG_SPKALC_COMP		0x43
 #define M98088_REG_PWRLMT_CFG		0x44
 #define M98088_REG_PWRLMT_TIME		0x45
 #define M98088_REG_THDLMT_CFG		0x46
 #define M98088_REG_CFG_AUDIO_IN		0x47
-#define M98088_REG_CFG_MIC		0X48
-#define M98088_REG_CFG_LEVEL		0X49
+#define M98088_REG_CFG_MIC		0x48
+#define M98088_REG_CFG_LEVEL		0x49
 #define M98088_REG_CFG_BYPASS		0x4a
 #define M98088_REG_CFG_JACKDET		0x4b
-#define M98088_REG_PWR_EN_IN		0X4c
+#define M98088_REG_PWR_EN_IN		0x4c
 #define M98088_REG_PWR_EN_OUT		0x4d
-#define M98088_REG_BIAS_CNTL		0X4e
-#define M98088_REG_DAC_BIAS1		0X4f
-#define M98088_REG_DAC_BIAS2		0X50
-#define M98088_REG_PWR_SYS		0X51
+#define M98088_REG_BIAS_CNTL		0x4e
+#define M98088_REG_DAC_BIAS1		0x4f
+#define M98088_REG_DAC_BIAS2		0x50
+#define M98088_REG_PWR_SYS		0x51
 #define M98088_REG_DAI1_EQ_BASE		0x52
 #define M98088_REG_DAI2_EQ_BASE		0x84
 #define M98088_REG_DAI1_BIQUAD_BASE	0xb6
diff --git a/drivers/sound/max98095.h b/drivers/sound/max98095.h
index 1521f3f02f9..009164d85d2 100644
--- a/drivers/sound/max98095.h
+++ b/drivers/sound/max98095.h
@@ -176,7 +176,7 @@ enum en_max_audio_interface {
 #define M98095_0FF_REV_ID		0xFF
 
 #define M98095_REG_CNT			(0xFF+1)
-#define M98095_REG_MAX_CACHED		0X97
+#define M98095_REG_MAX_CACHED		0x97
 
 /* MAX98095 Registers Bit Fields */
 
diff --git a/drivers/video/bridge/dp501.c b/drivers/video/bridge/dp501.c
index 9937cfe095b..0ad589304aa 100644
--- a/drivers/video/bridge/dp501.c
+++ b/drivers/video/bridge/dp501.c
@@ -99,7 +99,7 @@
 #define SD_DB15			0x4F
 
 /* Aux Channel and PCS */
-#define DPCD_REV		0X50
+#define DPCD_REV		0x50
 #define MAX_LINK_RATE		0x51
 #define MAX_LANE_COUNT		0x52
 #define MAX_DOWNSPREAD		0x53
diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c
index 2491a32810e..f0220e4cc07 100644
--- a/drivers/video/hx8238d.c
+++ b/drivers/video/hx8238d.c
@@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define HX8238D_OUTPUT_CTRL_ADDR        0x01
 #define HX8238D_LCD_AC_CTRL_ADDR        0x02
 #define HX8238D_POWER_CTRL_1_ADDR       0x03
-#define HX8238D_DATA_CLR_CTRL_ADDR      0X04
+#define HX8238D_DATA_CLR_CTRL_ADDR      0x04
 #define HX8238D_FUNCTION_CTRL_ADDR      0x05
 #define HX8238D_LED_CTRL_ADDR           0x08
 #define HX8238D_CONT_BRIGHT_CTRL_ADDR   0x0A
diff --git a/drivers/video/zynqmp/zynqmp_dpsub.h b/drivers/video/zynqmp/zynqmp_dpsub.h
index 7d2737e31aa..dc549559cae 100644
--- a/drivers/video/zynqmp/zynqmp_dpsub.h
+++ b/drivers/video/zynqmp/zynqmp_dpsub.h
@@ -553,7 +553,7 @@ struct zynqmp_dpsub_priv {
 #define DPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT				18
 #define DPDMA_DESCRIPTOR_SRC_ADDR_WIDTH					32U
 #define DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT			16U
-#define DPDMA_CH0_DSCR_STRT_ADDR					0X0204U
+#define DPDMA_CH0_DSCR_STRT_ADDR					0x0204U
 #define DPDMA_CH_OFFSET							0x100U
 #define DPDMA_CH0_CNTL							0x0218U
 #define DPDMA_CH3_CNTL							0x0518U
-- 
2.49.0

[PATCH v1 4/7] tools: use lowercase hex prefix style

[E Shattow]

Use consistent lowercase hex prefix style in tools/*

Signed-off-by: E Shattow <e@freeshell.de>
---
 tools/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/Kconfig b/tools/Kconfig
index 8e272ee99a8..652b0f22557 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -137,7 +137,7 @@ config DEVICE_TYPE
 	default 0x01
 	depends on FSPI_CONF_HEADER
 	help
-	  Flash type: Serial NOR (0X01) and Serial NAND (0x02)
+	  Flash type: Serial NOR (0x01) and Serial NAND (0x02)
 
 config FLASH_PAD_TYPE
 	hex "Flash Pad Type"
-- 
2.49.0

[PATCH v1 5/7] lib: use lowercase hex prefix style

[E Shattow]

Use consistent lowercase hex prefix style in lib/*

Signed-off-by: E Shattow <e@freeshell.de>
---
 .../external/mbedtls/library/ecp_curves_new.c | 46 +++++++++----------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/lib/mbedtls/external/mbedtls/library/ecp_curves_new.c b/lib/mbedtls/external/mbedtls/library/ecp_curves_new.c
index 035b23a1b41..0275661887b 100644
--- a/lib/mbedtls/external/mbedtls/library/ecp_curves_new.c
+++ b/lib/mbedtls/external/mbedtls/library/ecp_curves_new.c
@@ -4644,17 +4644,17 @@ static const mbedtls_mpi_sint curve25519_a24 = 0x01DB42;
 
 /* P = 2^255 - 19 */
 static const mbedtls_mpi_uint curve25519_p[] = {
-    MBEDTLS_BYTES_TO_T_UINT_8(0xED, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0X7F)
+    MBEDTLS_BYTES_TO_T_UINT_8(0xED, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F)
 };
 
 /* N = 2^252 + 27742317777372353535851937790883648493 */
 static const mbedtls_mpi_uint curve25519_n[] = {
-    MBEDTLS_BYTES_TO_T_UINT_8(0XED, 0XD3, 0XF5, 0X5C, 0X1A, 0X63, 0X12, 0X58),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XD6, 0X9C, 0XF7, 0XA2, 0XDE, 0XF9, 0XDE, 0X14),
-    MBEDTLS_BYTES_TO_T_UINT_8(0X00, 0X00, 0X00, 0X00, 0x00, 0x00, 0x00, 0x00),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xED, 0xD3, 0xF5, 0x5C, 0x1A, 0x63, 0x12, 0x58),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xD6, 0x9C, 0xF7, 0xA2, 0xDE, 0xF9, 0xDE, 0x14),
+    MBEDTLS_BYTES_TO_T_UINT_8(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
     MBEDTLS_BYTES_TO_T_UINT_8(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10)
 };
 
@@ -4698,26 +4698,26 @@ static const mbedtls_mpi_sint curve448_a24 = 0x98AA;
 
 /* P = 2^448 - 2^224 - 1 */
 static const mbedtls_mpi_uint curve448_p[] = {
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFE, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00)
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
 };
 
 /* N = 2^446 - 13818066809895115352007386748515426880336692474882178609894547503885 */
 static const mbedtls_mpi_uint curve448_n[] = {
-    MBEDTLS_BYTES_TO_T_UINT_8(0XF3, 0X44, 0X58, 0XAB, 0X92, 0XC2, 0X78, 0X23),
-    MBEDTLS_BYTES_TO_T_UINT_8(0X55, 0X8F, 0XC5, 0X8D, 0X72, 0XC2, 0X6C, 0X21),
-    MBEDTLS_BYTES_TO_T_UINT_8(0X90, 0X36, 0XD6, 0XAE, 0X49, 0XDB, 0X4E, 0XC4),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XE9, 0X23, 0XCA, 0X7C, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
-    MBEDTLS_BYTES_TO_T_UINT_8(0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0X3F),
-    MBEDTLS_BYTES_TO_T_UINT_8(0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00)
+    MBEDTLS_BYTES_TO_T_UINT_8(0xF3, 0x44, 0x58, 0xAB, 0x92, 0xC2, 0x78, 0x23),
+    MBEDTLS_BYTES_TO_T_UINT_8(0x55, 0x8F, 0xC5, 0x8D, 0x72, 0xC2, 0x6C, 0x21),
+    MBEDTLS_BYTES_TO_T_UINT_8(0x90, 0x36, 0xD6, 0xAE, 0x49, 0xDB, 0x4E, 0xC4),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xE9, 0x23, 0xCA, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF),
+    MBEDTLS_BYTES_TO_T_UINT_8(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x3F),
+    MBEDTLS_BYTES_TO_T_UINT_8(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
 };
 
 /*
-- 
2.49.0

[PATCH v1 6/7] arch: use lowercase hex prefix style

[E Shattow]

Use consistent lowercase hex prefix style in arch/*

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/arm/dts/fsl-imx8qxp-ai_ml.dts            | 16 +++++++--------
 arch/arm/dts/hi3660.dtsi                      |  2 +-
 arch/arm/dts/imx7-colibri.dtsi                |  2 +-
 .../asm/arch-fsl-layerscape/immap_lsch3.h     |  2 +-
 arch/arm/include/asm/arch-mx6/mx6sl_pins.h    |  8 ++++----
 arch/arm/include/asm/arch-rockchip/cru_px30.h |  6 +++---
 .../arm/include/asm/arch-rockchip/f_rockusb.h |  2 +-
 .../include/asm/arch-rockchip/sdram_px30.h    |  2 +-
 .../include/asm/arch-rockchip/sdram_rk3328.h  |  2 +-
 .../include/asm/arch-rockchip/sdram_rv1126.h  |  2 +-
 arch/arm/include/asm/iproc-common/sysmap.h    | 20 +++++++++----------
 arch/arm/mach-at91/include/mach/at91_wdt.h    |  2 +-
 arch/arm/mach-exynos/include/mach/dsim.h      |  2 +-
 arch/arm/mach-imx/iomux-v3.c                  |  2 +-
 .../mach-keystone/include/mach/hardware-k2g.h |  4 ++--
 arch/arm/mach-kirkwood/include/mach/mpp.h     |  2 +-
 arch/arm/mach-omap2/lowlevel_init.S           |  2 +-
 arch/arm/mach-sc5xx/init/dmcinit.c            |  2 +-
 .../include/mach/clock_manager_s10.h          |  6 +++---
 arch/arm/mach-uniphier/bcu/bcu-ld4.c          |  2 +-
 arch/arm/mach-zynqmp/include/mach/hardware.h  |  2 +-
 arch/mips/mach-jz47xx/jz4780/pll.c            |  2 +-
 arch/powerpc/include/asm/immap_85xx.h         |  6 +++---
 arch/powerpc/include/asm/processor.h          |  4 ++--
 24 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml.dts b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
index aa85caaff58..be94767fa94 100644
--- a/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
+++ b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
@@ -130,29 +130,29 @@
 
 	pinctrl_lpuart0: lpuart0grp {
 		fsl,pins = <
-			SC_P_UART0_RX_ADMA_UART0_RX			0X06000020
-			SC_P_UART0_TX_ADMA_UART0_TX			0X06000020
+			SC_P_UART0_RX_ADMA_UART0_RX			0x06000020
+			SC_P_UART0_TX_ADMA_UART0_TX			0x06000020
 		>;
 	};
 
 	pinctrl_lpuart1: lpuart1grp {
 		fsl,pins = <
-			SC_P_UART1_RX_ADMA_UART1_RX			0X06000020
-			SC_P_UART1_TX_ADMA_UART1_TX			0X06000020
+			SC_P_UART1_RX_ADMA_UART1_RX			0x06000020
+			SC_P_UART1_TX_ADMA_UART1_TX			0x06000020
 		>;
 	};
 
 	pinctrl_lpuart2: lpuart2grp {
 		fsl,pins = <
-			SC_P_UART2_RX_ADMA_UART2_RX			0X06000020
-			SC_P_UART2_TX_ADMA_UART2_TX			0X06000020
+			SC_P_UART2_RX_ADMA_UART2_RX			0x06000020
+			SC_P_UART2_TX_ADMA_UART2_TX			0x06000020
 		>;
 	};
 
 	pinctrl_lpuart3: lpuart3grp {
 		fsl,pins = <
-			SC_P_FLEXCAN2_RX_ADMA_UART3_RX			0X06000020
-			SC_P_FLEXCAN2_TX_ADMA_UART3_TX			0X06000020
+			SC_P_FLEXCAN2_RX_ADMA_UART3_RX			0x06000020
+			SC_P_FLEXCAN2_TX_ADMA_UART3_TX			0x06000020
 		>;
 	};
 
diff --git a/arch/arm/dts/hi3660.dtsi b/arch/arm/dts/hi3660.dtsi
index 028f4db60d2..7cc1e1b6279 100644
--- a/arch/arm/dts/hi3660.dtsi
+++ b/arch/arm/dts/hi3660.dtsi
@@ -580,7 +580,7 @@
 
 		rtc0: rtc@fff04000 {
 			compatible = "arm,pl031", "arm,primecell";
-			reg = <0x0 0Xfff04000 0x0 0x1000>;
+			reg = <0x0 0xfff04000 0x0 0x1000>;
 			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&crg_ctrl HI3660_PCLK>;
 			clock-names = "apb_pclk";
diff --git a/arch/arm/dts/imx7-colibri.dtsi b/arch/arm/dts/imx7-colibri.dtsi
index a8c31ee6562..4c0b5ec6c61 100644
--- a/arch/arm/dts/imx7-colibri.dtsi
+++ b/arch/arm/dts/imx7-colibri.dtsi
@@ -669,7 +669,7 @@
 
 	pinctrl_can_int: canintgrp {
 		fsl,pins = <
-			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0X14 /* SODIMM 73 */
+			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x14 /* SODIMM 73 */
 		>;
 	};
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 306f797f7a8..86d295c1a8d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -241,7 +241,7 @@
 #define DCFG_RCWSR15			0x138
 #define DCFG_RCWSR15_IFCGRPABASE_QSPI	0x3
 
-#define DCFG_DCSR_BASE		0X700100000ULL
+#define DCFG_DCSR_BASE		0x700100000ULL
 #define DCFG_DCSR_PORCR1		0x000
 
 /* Interrupt Sampling Control */
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 01b14d73dc9..699c951b1b9 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -31,10 +31,10 @@ enum {
 	MX6_PAD_SD2_DAT1__USDHC2_DAT1				= IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
 	MX6_PAD_SD2_DAT2__USDHC2_DAT2				= IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
 	MX6_PAD_SD2_DAT3__USDHC2_DAT3				= IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT4__USDHC2_DAT4				= IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0),
-	MX6_PAD_SD2_DAT5__USDHC2_DAT5				= IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0),
-	MX6_PAD_SD2_DAT6__USDHC2_DAT6				= IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0),
-	MX6_PAD_SD2_DAT7__USDHC2_DAT7				= IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0),
+	MX6_PAD_SD2_DAT4__USDHC2_DAT4				= IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT5__USDHC2_DAT5				= IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT6__USDHC2_DAT6				= IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT7__USDHC2_DAT7				= IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, 0),
 	MX6_PAD_SD2_DAT7__GPIO_5_0					= IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
 	MX6_PAD_SD2_RST__USDHC2_RST				= IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0),
 	MX6_PAD_SD3_CLK__USDHC3_CLK					= IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h
index 504459bd93d..408fdd66635 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h
@@ -299,9 +299,9 @@ enum {
 
 	/* CRU_CLK_SEL30_CON */
 	CLK_I2S1_DIV_CON_MASK	= 0x7f,
-	CLK_I2S1_PLL_SEL_MASK	= 0X1 << 8,
-	CLK_I2S1_PLL_SEL_GPLL	= 0X0 << 8,
-	CLK_I2S1_PLL_SEL_NPLL	= 0X1 << 8,
+	CLK_I2S1_PLL_SEL_MASK	= 0x1 << 8,
+	CLK_I2S1_PLL_SEL_GPLL	= 0x0 << 8,
+	CLK_I2S1_PLL_SEL_NPLL	= 0x1 << 8,
 	CLK_I2S1_SEL_MASK	= 0x3 << 10,
 	CLK_I2S1_SEL_I2S1	= 0x0 << 10,
 	CLK_I2S1_SEL_FRAC	= 0x1 << 10,
diff --git a/arch/arm/include/asm/arch-rockchip/f_rockusb.h b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
index e9c7f793391..9abb3b16c42 100644
--- a/arch/arm/include/asm/arch-rockchip/f_rockusb.h
+++ b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
@@ -65,7 +65,7 @@ K_FW_SPI_READ_10 = 0x21,
 K_FW_SPI_WRITE_10 = 0x22,
 K_FW_LBA_ERASE_10 = 0x25,
 
-K_FW_SESSION = 0X30,
+K_FW_SESSION = 0x30,
 K_FW_RESET = 0xff,
 };
 
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_px30.h
index 2ab8e97ae1d..bf0cd01e7cc 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_px30.h
@@ -20,7 +20,7 @@
 
 /* DDR GRF */
 #define DDR_GRF_CON(n)			(0 + (n) * 4)
-#define DDR_GRF_STATUS_BASE		(0X100)
+#define DDR_GRF_STATUS_BASE		(0x100)
 #define DDR_GRF_STATUS(n)		(DDR_GRF_STATUS_BASE + (n) * 4)
 #define DDR_GRF_LP_CON			(0x20)
 
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
index 10923505d6e..454f9ca8878 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
@@ -32,7 +32,7 @@
 
 /* DDR GRF */
 #define DDR_GRF_CON(n)		(0 + (n) * 4)
-#define DDR_GRF_STATUS_BASE	(0X100)
+#define DDR_GRF_STATUS_BASE	(0x100)
 #define DDR_GRF_STATUS(n)	(DDR_GRF_STATUS_BASE + (n) * 4)
 
 /* CRU_SOFTRESET_CON5 */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
index 6a07436059c..9b65bad2581 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
@@ -185,7 +185,7 @@
 
 /* DDR GRF */
 #define DDR_GRF_CON(n)			(0 + (n) * 4)
-#define DDR_GRF_STATUS_BASE		(0X100)
+#define DDR_GRF_STATUS_BASE		(0x100)
 #define DDR_GRF_STATUS(n)		(DDR_GRF_STATUS_BASE + (n) * 4)
 #define DDR_GRF_LP_CON			(0x20)
 
diff --git a/arch/arm/include/asm/iproc-common/sysmap.h b/arch/arm/include/asm/iproc-common/sysmap.h
index efd2f35f212..c071e9ea53f 100644
--- a/arch/arm/include/asm/iproc-common/sysmap.h
+++ b/arch/arm/include/asm/iproc-common/sysmap.h
@@ -6,17 +6,17 @@
 #ifndef __SYSMAP_H
 #define __SYSMAP_H
 
-#define IHOST_PROC_CLK_PLLARMA					0X19000C00
-#define IHOST_PROC_CLK_PLLARMB					0X19000C04
+#define IHOST_PROC_CLK_PLLARMA					0x19000C00
+#define IHOST_PROC_CLK_PLLARMB					0x19000C04
 #define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R				24
 
-#define IHOST_PROC_CLK_WR_ACCESS				0X19000000
-#define IHOST_PROC_CLK_POLICY_FREQ				0X19000008
+#define IHOST_PROC_CLK_WR_ACCESS				0x19000000
+#define IHOST_PROC_CLK_POLICY_FREQ				0x19000008
 #define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE			31
 #define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R			24
 #define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R			16
 #define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R			 8
-#define IHOST_PROC_CLK_POLICY_CTL				0X1900000C
+#define IHOST_PROC_CLK_POLICY_CTL				0x1900000C
 #define IHOST_PROC_CLK_POLICY_CTL__GO					 0
 #define IHOST_PROC_CLK_POLICY_CTL__GO_AC				 1
 #define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R			 0
@@ -26,11 +26,11 @@
 #define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R			 8
 #define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB			 1
 #define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB			 0
-#define IHOST_PROC_CLK_CORE0_CLKGATE				0X19000200
-#define IHOST_PROC_CLK_CORE1_CLKGATE				0X19000204
-#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE			0X19000210
-#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE			0X19000300
-#define IHOST_PROC_CLK_APB0_CLKGATE				0X19000400
+#define IHOST_PROC_CLK_CORE0_CLKGATE				0x19000200
+#define IHOST_PROC_CLK_CORE1_CLKGATE				0x19000204
+#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE			0x19000210
+#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE			0x19000300
+#define IHOST_PROC_CLK_APB0_CLKGATE				0x19000400
 #define IPROC_CLKCT_HDELAY_SW_EN				0x00000303
 
 #define IPROC_REG_WRITE_ACCESS					0x00a5a501
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
index 8ef8e007d77..25d95fab1f8 100644
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
@@ -38,7 +38,7 @@ struct at91_wdt_priv {
 #define AT91_WDT_CR_KEY			0xa5000000	/* KEY Password */
 
 /* Watchdog Mode Register*/
-#define AT91_WDT_MR			0X04
+#define AT91_WDT_MR			0x04
 #define AT91_WDT_MR_WDV(x)		(x & 0xfff)
 #define AT91_WDT_MR_WDFIEN		0x00001000
 #define AT91_WDT_MR_WDRSTEN		0x00002000
diff --git a/arch/arm/mach-exynos/include/mach/dsim.h b/arch/arm/mach-exynos/include/mach/dsim.h
index 15671b603c3..de6c2d29871 100644
--- a/arch/arm/mach-exynos/include/mach/dsim.h
+++ b/arch/arm/mach-exynos/include/mach/dsim.h
@@ -101,7 +101,7 @@ struct exynos_mipi_dsim {
 /* EXYNOS_DSIM_MDRESOL */
 #define DSIM_MAIN_STAND_BY		(1 << 31)
 #define DSIM_MAIN_VRESOL(x)		(((x) & 0x7ff) << 16)
-#define DSIM_MAIN_HRESOL(x)		(((x) & 0X7ff) << 0)
+#define DSIM_MAIN_HRESOL(x)		(((x) & 0x7ff) << 0)
 
 /* EXYNOS_DSIM_MVPORCH */
 #define DSIM_CMD_ALLOW_SHIFT		(28)
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index c134e95ed78..22ffbcaffd9 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -142,6 +142,6 @@ void imx_iomux_gpio_set_direction(unsigned int gpio,
 void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
 {
 	*gpio_state = readl(base + (gpio << 2)) &
-		((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
+		((0x07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
 }
 #endif
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
index 971c081bb3c..482995fc8ba 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -67,8 +67,8 @@
 /* NETCP */
 #define KS2_NETCP_BASE			0x04000000
 
-#define K2G_GPIO0_BASE			0X02603000
-#define K2G_GPIO1_BASE			0X0260a000
+#define K2G_GPIO0_BASE			0x02603000
+#define K2G_GPIO1_BASE			0x0260a000
 #define K2G_GPIO0_BANK0_BASE		K2G_GPIO0_BASE + 0x10
 #define K2G_GPIO1_BANK2_BASE		K2G_GPIO1_BASE + 0x38
 #define K2G_GPIO_DIR_OFFSET		0x0
diff --git a/arch/arm/mach-kirkwood/include/mach/mpp.h b/arch/arm/mach-kirkwood/include/mach/mpp.h
index e2757942590..f50156b3357 100644
--- a/arch/arm/mach-kirkwood/include/mach/mpp.h
+++ b/arch/arm/mach-kirkwood/include/mach/mpp.h
@@ -89,7 +89,7 @@
 
 #define MPP10_GPO		MPP( 10, 0x0, 0, 1, 1,   1,   1,   1    )
 #define MPP10_SPI_SCK		MPP( 10, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP10_UART0_TXD		MPP( 10, 0X3, 0, 1, 1,   1,   1,   1    )
+#define MPP10_UART0_TXD		MPP( 10, 0x3, 0, 1, 1,   1,   1,   1    )
 #define MPP10_SATA1_ACTn	MPP( 10, 0x5, 0, 1, 0,   0,   1,   1    )
 #define MPP10_PTP_TRIG_GEN	MPP( 10, 0xc, 0, 1, 1,   1,   1,   1    )
 
diff --git a/arch/arm/mach-omap2/lowlevel_init.S b/arch/arm/mach-omap2/lowlevel_init.S
index 1a55295f9de..e977805bd03 100644
--- a/arch/arm/mach-omap2/lowlevel_init.S
+++ b/arch/arm/mach-omap2/lowlevel_init.S
@@ -39,7 +39,7 @@ restore_from_hyp:
 	adr	r0, save_sp
 	ldr	sp, [r0]
 	MRC p15, 4, R0, c1, c0, 0
-	ldr     r1, =0X1004	@Set cache enable bits for hypervisor mode
+	ldr     r1, =0x1004	@Set cache enable bits for hypervisor mode
 	orr     r0, r0, r1
 	MCR p15, 4, R0, c1, c0, 0
 	b	switch_to_hypervisor_ret
diff --git a/arch/arm/mach-sc5xx/init/dmcinit.c b/arch/arm/mach-sc5xx/init/dmcinit.c
index e375b5c9dfa..30b77aee459 100644
--- a/arch/arm/mach-sc5xx/init/dmcinit.c
+++ b/arch/arm/mach-sc5xx/init/dmcinit.c
@@ -367,7 +367,7 @@ static inline void calibration_legacy(void)
 	 */
 	if (dmc.ddr_mode == DDR3_MODE ||
 	    dmc.ddr_mode == DDR2_MODE) {
-		writel(0XFC000000, dmc.reg + REG_DMC_PHY_CTL2);
+		writel(0xFC000000, dmc.reg + REG_DMC_PHY_CTL2);
 		writel(0x0000000f, dmc.reg + REG_DMC_PHY_CTL0);
 	}
 
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 18921169a6d..5dcbda9473e 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -120,12 +120,12 @@ void cm_basic_init(const struct cm_config * const cfg);
 
 #define CLKMGR_PLLGLOB_PD_MASK				0x00000001
 #define CLKMGR_PLLGLOB_RST_MASK				0x00000002
-#define CLKMGR_PLLGLOB_VCO_PSRC_MASK			0X3
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK			0x3
 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET			16
 #define CLKMGR_VCO_PSRC_EOSC1				0
 #define CLKMGR_VCO_PSRC_INTOSC				1
 #define CLKMGR_VCO_PSRC_F2S				2
-#define CLKMGR_PLLGLOB_REFCLKDIV_MASK			0X3f
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK			0x3f
 #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET			8
 
 #define CLKMGR_CLKSRC_MASK				0x7
@@ -152,7 +152,7 @@ void cm_basic_init(const struct cm_config * const cfg);
 #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET			26
 #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET			28
 
-#define CLKMGR_NOCDIV_L4SPCLK_MASK			0X3
+#define CLKMGR_NOCDIV_L4SPCLK_MASK			0x3
 #define CLKMGR_NOCDIV_DIV1				0
 #define CLKMGR_NOCDIV_DIV2				1
 #define CLKMGR_NOCDIV_DIV4				2
diff --git a/arch/arm/mach-uniphier/bcu/bcu-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ld4.c
index ea6088ba1cb..08c41fa6d4d 100644
--- a/arch/arm/mach-uniphier/bcu/bcu-ld4.c
+++ b/arch/arm/mach-uniphier/bcu/bcu-ld4.c
@@ -20,7 +20,7 @@ void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd)
 	writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
 	writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
 	writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
-	writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
+	writel(0x11111111, BCSCR5); /* 0xe0000000-0xffffffff: IPPC/IPPD-bus */
 
 	/* Specify DDR channel */
 	shift = bd->dram_ch[0].size / 0x04000000 * 4;
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index 3c372bd6dcf..02bbc54ff0f 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -19,7 +19,7 @@
 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT	0
 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT	8
 
-#define ZYNQMP_AMS_PS_SYSMON_BASEADDR      0XFFA50800
+#define ZYNQMP_AMS_PS_SYSMON_BASEADDR      0xFFA50800
 #define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \
 							    + 0x00000114)
 #define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210
diff --git a/arch/mips/mach-jz47xx/jz4780/pll.c b/arch/mips/mach-jz47xx/jz4780/pll.c
index 8ef00f99a10..0ff717b4595 100644
--- a/arch/mips/mach-jz47xx/jz4780/pll.c
+++ b/arch/mips/mach-jz47xx/jz4780/pll.c
@@ -327,7 +327,7 @@
 /* BCH clock divider register */
 #define CPM_BCHCDR_BPCS_BIT		30
 #define CPM_BCHCDR_BPCS_MASK		(0x3 << CPM_BCHCDR_BPCS_BIT)
-#define CPM_BCHCDR_BPCS_STOP		(0X0 << CPM_BCHCDR_BPCS_BIT)
+#define CPM_BCHCDR_BPCS_STOP		(0x0 << CPM_BCHCDR_BPCS_BIT)
 #define CPM_BCHCDR_BPCS_SRC_CLK		(0x1 << CPM_BCHCDR_BPCS_BIT)
 #define CPM_BCHCDR_BPCS_MPLL		(0x2 << CPM_BCHCDR_BPCS_BIT)
 #define CPM_BCHCDR_BPCS_EPLL		(0x3 << CPM_BCHCDR_BPCS_BIT)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7293720fb3c..3565a287154 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2027,8 +2027,8 @@ typedef struct ccsr_gur {
 #endif
 #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
 #if defined(CONFIG_ARCH_BSC9131)
-#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD		0X40000000
-#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS		0X80000000
+#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD		0x40000000
+#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS		0x80000000
 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42		0xC0000000
 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2		0x10000000
 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK		0x20000000
@@ -2727,7 +2727,7 @@ struct ccsr_cluster_l2 {
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET)
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
-#define	CFG_SYS_DCSR_DCFG_OFFSET	0X20000
+#define	CFG_SYS_DCSR_DCFG_OFFSET	0x20000
 struct dcsr_dcfg_regs {
 	u8  res_0[0x520];
 	u32 ecccr1;
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index f7e1a807746..2357734a5be 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1053,7 +1053,7 @@
 #define SVR_P4080	0x820000
 #define SVR_P5010	0x822100
 #define SVR_P5020	0x822000
-#define SVR_P5021	0X820500
+#define SVR_P5021	0x820500
 #define SVR_P5040	0x820400
 #define SVR_T4240	0x824000
 #define SVR_T4120	0x824001
@@ -1062,7 +1062,7 @@
 #define SVR_C291	0x850000
 #define SVR_C292	0x850020
 #define SVR_C293	0x850030
-#define SVR_B4860	0X868000
+#define SVR_B4860	0x868000
 #define SVR_G4860	0x868001
 #define SVR_B4460	0x868003
 #define SVR_B4440	0x868100
-- 
2.49.0

[PATCH v1 7/7] include: use lowercase hex prefix style

[E Shattow]

Use consistent lowercase hex prefix style in include/*

Signed-off-by: E Shattow <e@freeshell.de>
---
 include/fsl_esdhc.h     | 2 +-
 include/fsl_esdhc_imx.h | 2 +-
 include/mc13892.h       | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 7ab1460abc6..d1f441e19b5 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -88,7 +88,7 @@
 #define PRSSTAT_CINS		(0x00010000)
 #define PRSSTAT_BREN		(0x00000800)
 #define PRSSTAT_BWEN		(0x00000400)
-#define PRSSTAT_SDSTB		(0X00000008)
+#define PRSSTAT_SDSTB		(0x00000008)
 #define PRSSTAT_DLA		(0x00000004)
 #define PRSSTAT_CICHB		(0x00000002)
 #define PRSSTAT_CIDHB		(0x00000001)
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index 8612b56609e..cd8ed833771 100644
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -97,7 +97,7 @@
 #define PRSSTAT_BREN		(0x00000800)
 #define PRSSTAT_BWEN		(0x00000400)
 #define PRSSTAT_SDOFF		(0x00000080)
-#define PRSSTAT_SDSTB		(0X00000008)
+#define PRSSTAT_SDSTB		(0x00000008)
 #define PRSSTAT_DLA		(0x00000004)
 #define PRSSTAT_CICHB		(0x00000002)
 #define PRSSTAT_CIDHB		(0x00000001)
diff --git a/include/mc13892.h b/include/mc13892.h
index d9ef53b1e48..a044a4c606d 100644
--- a/include/mc13892.h
+++ b/include/mc13892.h
@@ -161,7 +161,7 @@
 /* SWx Output Volts */
 #define SWX_OUT_MASK	0x1F
 #define SWX_OUT_1_25	0x1A
-#define SWX_OUT_1_30    0X1C
+#define SWX_OUT_1_30    0x1C
 
 /* Buck Switchers (SW1,2,3,4) Output Voltage */
 /*
-- 
2.49.0

Re: [PATCH v1 0/7] Hex value prefix case cleanup

[Tom Rini]

On Fri, 06 Jun 2025 15:44:55 -0700, E Shattow wrote:

> Make consistent use of lowercase hexadecimal prefix '0x' throughout U-Boot.
> 
> There are a few remaining uses of uppercase 'X' to denote hexadecimal prefix
> or placeholder in documentation and error messages.
> 
> External devicetree-rebasing dts/upstream and the generated code of
> xilinx/zynq are ignored for the series.
> 
> [...]

Applied to u-boot/next, thanks!

[1/7] configs: use lowercase hex prefix style
      commit: 9f208a3e709f8201f0d7dd6fe23c789430ba6c1f
[2/7] board: use lowercase hex prefix style
      commit: ba7634c6b6f1924d87af001dfdefdbced34442e9
[3/7] drivers: use lowercase hex prefix style
      commit: 449a5566522f07b4c8d58f3a6bdc36a74400e672
[4/7] tools: use lowercase hex prefix style
      commit: c5824a1b3d9776632e5c57c2f212819e2f2c8532
[5/7] lib: use lowercase hex prefix style
      commit: d1aacc9c787e67314dd24e8f104a67d773e33c98
[6/7] arch: use lowercase hex prefix style
      commit: 58bcf9ab19290442019bfa80a66a535252f341fd
[7/7] include: use lowercase hex prefix style
      commit: 0230ad1c30a405c807dad5f78c95c57704234ffd
-- 
Tom

Re: [PATCH v1 3/7] drivers: use lowercase hex prefix style

[Patrick DELAUNAY]

Hi,

On 6/7/25 00:44, E Shattow wrote:
> Use consistent lowercase hex prefix style in drivers/*
>
> Does not change hex prefix case in allcaps uppercase style error messages
>
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
>   drivers/ata/dwc_ahsata_priv.h             |  4 +-
>   drivers/clk/renesas/r8a774a1-cpg-mssr.c   |  2 +-
>   drivers/clk/stm32/clk-stm32mp1.c          |  2 +-
>   drivers/ddr/altera/iossm_mailbox.c        |  2 +-
>   drivers/mmc/sdhci-cadence6.c              |  2 +-
>   drivers/mmc/zynq_sdhci.c                  |  2 +-
>   drivers/mtd/nand/raw/lpc32xx_nand_mlc.c   |  4 +-
>   drivers/net/fsl-mc/mc.c                   |  2 +-
>   drivers/net/phy/ca_phy.c                  |  2 +-
>   drivers/phy/rockchip/phy-rockchip-typec.c |  2 +-
>   drivers/power/regulator/act8846.c         |  4 +-
>   drivers/ram/k3-ddrss/k3-ddrss.c           |  2 +-
>   drivers/ram/octeon/octeon3_lmc.c          |  2 +-
>   drivers/sound/max98088.h                  | 50 +++++++++++------------
>   drivers/sound/max98095.h                  |  2 +-
>   drivers/video/bridge/dp501.c              |  2 +-
>   drivers/video/hx8238d.c                   |  2 +-
>   drivers/video/zynqmp/zynqmp_dpsub.h       |  2 +-
>   18 files changed, 45 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/ata/dwc_ahsata_priv.h b/drivers/ata/dwc_ahsata_priv.h
> index 0c2cd5446b5..f2a118420f9 100644
> --- a/drivers/ata/dwc_ahsata_priv.h
> +++ b/drivers/ata/dwc_ahsata_priv.h
> @@ -117,8 +117,8 @@
>   #define SATA_HOST_GPARAM1R_PHY_TYPE	0x00001000
>   #define SATA_HOST_GPARAM1R_RETURN_ERR	0x00000400
>   #define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK	0x00000300
> -#define SATA_HOST_GPARAM1R_S_HADDR	0X00000080
> -#define SATA_HOST_GPARAM1R_M_HADDR	0X00000040
> +#define SATA_HOST_GPARAM1R_S_HADDR	0x00000080
> +#define SATA_HOST_GPARAM1R_M_HADDR	0x00000040
>   
>   /* Global Parameter 2 Register */
...
> diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
> index 9cb69a01f7f..823ce132d0b 100644
> --- a/drivers/clk/stm32/clk-stm32mp1.c
> +++ b/drivers/clk/stm32/clk-stm32mp1.c
> @@ -117,7 +117,7 @@ DECLARE_GLOBAL_DATA_PTR;
>   #define RCC_DSICKSELR		0x924
>   #define RCC_ADCCKSELR		0x928
>   #define RCC_MP_APB1ENSETR	0xA00
> -#define RCC_MP_APB2ENSETR	0XA08
> +#define RCC_MP_APB2ENSETR	0xA08
>   #define RCC_MP_APB3ENSETR	0xA10
>   #define RCC_MP_AHB2ENSETR	0xA18
>   #define RCC_MP_AHB3ENSETR	0xA20

....


For stm32mp1 clock driver,


Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Thanks
Patrick