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From: Jonathan Cameron via <qemu-arm@nongnu.org>
To: Alireza Sanaee <alireza.sanaee@huawei.com>
Cc: <qemu-devel@nongnu.org>, <mst@redhat.com>, <anisinha@redhat.com>,
	<armbru@redhat.com>, <berrange@redhat.com>,
	<dapeng1.mi@linux.intel.com>, <eric.auger@redhat.com>,
	<farman@linux.ibm.com>, <gustavo.romero@linaro.org>,
	 <imammedo@redhat.com>, <jiangkunkun@huawei.com>,
	<linuxarm@huawei.com>, <maobibo@loongson.cn>,
	<mtosatti@redhat.com>, <peter.maydell@linaro.org>,
	<philmd@linaro.org>, <qemu-arm@nongnu.org>,
	<richard.henderson@linaro.org>,
	<shameerali.kolothum.thodi@huawei.com>,
	<shannon.zhaosl@gmail.com>, <yangyicong@hisilicon.com>,
	<zhao1.liu@intel.com>
Subject: Re: [PATCH v13 2/7] hw/core/machine: topology functions capabilities added
Date: Mon, 16 Jun 2025 13:47:54 +0100	[thread overview]
Message-ID: <20250616134754.00004530@huawei.com> (raw)
In-Reply-To: <20250611155618.351-3-alireza.sanaee@huawei.com>

On Wed, 11 Jun 2025 16:56:13 +0100
Alireza Sanaee <alireza.sanaee@huawei.com> wrote:

> Add two functions one of which finds the lowest level cache defined in
> the cache description input, and the other checks if caches are defined
> at a particular level.
> 
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> ---
>  hw/core/machine-smp.c | 52 +++++++++++++++++++++++++++++++++++++++++++
>  include/hw/boards.h   |  7 ++++++
>  2 files changed, 59 insertions(+)
> 
> diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
> index 0be0ac044c..a4d79e0aa4 100644
> --- a/hw/core/machine-smp.c
> +++ b/hw/core/machine-smp.c

> +
> +bool machine_check_cache_at_topo_level(const MachineState *ms,

Maybe avoid machine_check naming. It has too many other meanings!

machine_is_cache_at_topo_level() perhaps?

> +                                       CpuTopologyLevel level)
> +{
> +    if (machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3) == level ||
> +        machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2) == level ||
> +        machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I) == level ||
> +        machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D) == level) {
> +        return true;
> +    }
> +    return false;
> +}



WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Alireza Sanaee <alireza.sanaee@huawei.com>
Cc: <qemu-devel@nongnu.org>, <mst@redhat.com>, <anisinha@redhat.com>,
	<armbru@redhat.com>, <berrange@redhat.com>,
	<dapeng1.mi@linux.intel.com>, <eric.auger@redhat.com>,
	<farman@linux.ibm.com>, <gustavo.romero@linaro.org>,
	 <imammedo@redhat.com>, <jiangkunkun@huawei.com>,
	<linuxarm@huawei.com>, <maobibo@loongson.cn>,
	<mtosatti@redhat.com>, <peter.maydell@linaro.org>,
	<philmd@linaro.org>, <qemu-arm@nongnu.org>,
	<richard.henderson@linaro.org>,
	<shameerali.kolothum.thodi@huawei.com>,
	<shannon.zhaosl@gmail.com>, <yangyicong@hisilicon.com>,
	<zhao1.liu@intel.com>
Subject: Re: [PATCH v13 2/7] hw/core/machine: topology functions capabilities added
Date: Mon, 16 Jun 2025 13:47:54 +0100	[thread overview]
Message-ID: <20250616134754.00004530@huawei.com> (raw)
In-Reply-To: <20250611155618.351-3-alireza.sanaee@huawei.com>

On Wed, 11 Jun 2025 16:56:13 +0100
Alireza Sanaee <alireza.sanaee@huawei.com> wrote:

> Add two functions one of which finds the lowest level cache defined in
> the cache description input, and the other checks if caches are defined
> at a particular level.
> 
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> ---
>  hw/core/machine-smp.c | 52 +++++++++++++++++++++++++++++++++++++++++++
>  include/hw/boards.h   |  7 ++++++
>  2 files changed, 59 insertions(+)
> 
> diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
> index 0be0ac044c..a4d79e0aa4 100644
> --- a/hw/core/machine-smp.c
> +++ b/hw/core/machine-smp.c

> +
> +bool machine_check_cache_at_topo_level(const MachineState *ms,

Maybe avoid machine_check naming. It has too many other meanings!

machine_is_cache_at_topo_level() perhaps?

> +                                       CpuTopologyLevel level)
> +{
> +    if (machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3) == level ||
> +        machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2) == level ||
> +        machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I) == level ||
> +        machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D) == level) {
> +        return true;
> +    }
> +    return false;
> +}




  parent reply	other threads:[~2025-06-16 12:48 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-11 15:56 [PATCH v13 0/7] Specifying cache topology on ARM Alireza Sanaee via
2025-06-11 15:56 ` Alireza Sanaee via
2025-06-11 15:56 ` [PATCH v13 1/7] target/arm/tcg: increase cache level for cpu=max Alireza Sanaee via
2025-06-11 15:56   ` Alireza Sanaee via
2025-06-11 15:56 ` [PATCH v13 2/7] hw/core/machine: topology functions capabilities added Alireza Sanaee via
2025-06-11 15:56   ` Alireza Sanaee via
2025-06-13  3:11   ` Zhao Liu
2025-06-16 12:47   ` Jonathan Cameron via [this message]
2025-06-16 12:47     ` Jonathan Cameron via
2025-06-11 15:56 ` [PATCH v13 3/7] hw/arm/virt: add cache hierarchy to device tree Alireza Sanaee via
2025-06-11 15:56   ` Alireza Sanaee via
2025-06-11 15:56 ` [PATCH v13 4/7] bios-tables-test: prepare to change ARM ACPI virt PPTT Alireza Sanaee via
2025-06-11 15:56   ` Alireza Sanaee via
2025-06-11 15:56 ` [PATCH v13 5/7] hw/acpi: add cache hierarchy to pptt table Alireza Sanaee via
2025-06-11 15:56   ` Alireza Sanaee via
2025-06-11 15:56 ` [PATCH v13 6/7] tests/qtest/bios-table-test: testing new ARM ACPI PPTT topology Alireza Sanaee via
2025-06-11 15:56   ` Alireza Sanaee via
2025-06-11 15:56 ` [PATCH v13 7/7] Update the ACPI tables based on new aml-build.c Alireza Sanaee via
2025-06-11 15:56   ` Alireza Sanaee via

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