From: Bjorn Helgaas <helgaas@kernel.org>
To: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: Manivannan Sadhasivam <mani@kernel.org>,
bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be,
magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org,
p.zabel@pengutronix.de, linux-pci@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
john.madieu.xa@bp.renesas.com,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH v2 4/8] PCI: rzg3s-host: Add Initial PCIe Host Driver for Renesas RZ/G3S SoC
Date: Wed, 25 Jun 2025 12:54:41 -0500 [thread overview]
Message-ID: <20250625175441.GA1579685@bhelgaas> (raw)
In-Reply-To: <5ed851fd-6cdc-48f6-ae39-67c95e6ad6d0@tuxon.dev>
On Wed, Jun 25, 2025 at 04:07:58PM +0300, Claudiu Beznea wrote:
> On 18.06.2025 20:42, Manivannan Sadhasivam wrote:
> > On Fri, May 30, 2025 at 02:19:13PM +0300, Claudiu wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express
> >> Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions
> >> only as a root complex, with a single-lane (x1) configuration. The
> >> controller includes Type 1 configuration registers, as well as IP
> >> specific registers (called AXI registers) required for various adjustments.
> This is how HW manual suggest to do it. The manual is open, it can be
> downloaded from [1]. Chapter that describes the steps implemented here is
> 34.4.2.4 Issuing Special Requests.
>
> Steps to reach the HW manual:
> 1/ click "RZ/G3S Group User's Manual: Hardware" button
> 2/ click confirm
> 3/ open the archive
> 4/ go to r01uh1014ej0110-rzg3s-users-manual-hardware -> Deliverables
> 5/ open r01uh1014ej0110-rzg3s.pdf
Nice that the manual is public! URLs are a great invention; it's too
bad when we need directions for where to click, etc, in addition to
the URL. Maybe one or both of these URLs could be included in the
commit log.
> [1]
> https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11ghz-cpu-and-dual-core-cortex-m33-250mhz?queryID=695cc067c2d89e3f271d43656ede4d12
https://www.renesas.com/en/document/mah/rzg3s-group-users-manual-hardware?r=25458591
next prev parent reply other threads:[~2025-06-25 21:03 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-30 11:19 [PATCH v2 0/8] PCI: rzg3s-host: Add PCIe driver for Renesas RZ/G3S SoC Claudiu
2025-05-30 11:19 ` [PATCH v2 1/8] soc: renesas: rz-sysc: Add syscon/regmap support Claudiu
2025-05-30 11:19 ` [PATCH v2 2/8] clk: renesas: r9a08g045: Add clocks, resets and power domain support for the PCIe Claudiu
2025-05-30 11:19 ` [PATCH v2 3/8] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S Claudiu
2025-06-05 22:13 ` Rob Herring (Arm)
2025-06-17 17:04 ` Manivannan Sadhasivam
2025-05-30 11:19 ` [PATCH v2 4/8] PCI: rzg3s-host: Add Initial PCIe Host Driver for Renesas RZ/G3S SoC Claudiu
2025-06-02 16:18 ` Ilpo Järvinen
2025-06-05 10:37 ` Claudiu Beznea
2025-06-05 7:47 ` kernel test robot
2025-06-05 8:09 ` kernel test robot
2025-06-05 22:57 ` Bjorn Helgaas
2025-06-06 9:12 ` Claudiu Beznea
2025-06-18 17:42 ` Manivannan Sadhasivam
2025-06-20 19:35 ` Manivannan Sadhasivam
2025-06-25 13:08 ` Claudiu Beznea
2025-06-25 13:07 ` Claudiu Beznea
2025-06-25 17:54 ` Bjorn Helgaas [this message]
2025-05-30 11:19 ` [PATCH v2 5/8] arm64: dts: renesas: r9a08g045s33: Add PCIe node Claudiu
2025-05-30 11:19 ` [PATCH v2 6/8] arm64: dts: renesas: rzg3s-smarc-som: Update dma-ranges for PCIe Claudiu
2025-05-30 11:19 ` [PATCH v2 7/8] arm64: dts: renesas: rzg3s-smarc: Enable PCIe Claudiu
2025-05-30 11:19 ` [PATCH v2 8/8] arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC Claudiu
2025-06-02 7:16 ` [PATCH v2 0/8] PCI: rzg3s-host: Add PCIe driver for " Wolfram Sang
2025-07-15 14:46 ` Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250625175441.GA1579685@bhelgaas \
--to=helgaas@kernel.org \
--cc=bhelgaas@google.com \
--cc=claudiu.beznea.uj@bp.renesas.com \
--cc=claudiu.beznea@tuxon.dev \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=john.madieu.xa@bp.renesas.com \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=magnus.damm@gmail.com \
--cc=mani@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.