Re: [PATCH 1/1] dt-bindings: mtd: convert lpc32xx-slc.txt to yaml format

[Rob Herring <robh@kernel.org>]

On Mon, Jun 23, 2025 at 04:23:24PM -0400, Frank Li wrote:
> Convert lpc32xx-slc.txt to yaml format.
> 
> Additional changes:
> - add ref to nand-controller.yaml
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  .../devicetree/bindings/mtd/lpc32xx-slc.txt   |  52 ---------
>  .../bindings/mtd/nxp,lpc3220-slc.yaml         | 101 ++++++++++++++++++
>  2 files changed, 101 insertions(+), 52 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt
>  create mode 100644 Documentation/devicetree/bindings/mtd/nxp,lpc3220-slc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt
> deleted file mode 100644
> index 39f17630a3011..0000000000000
> --- a/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt
> +++ /dev/null
> @@ -1,52 +0,0 @@
> -NXP LPC32xx SoC NAND SLC controller
> -
> -Required properties:
> -- compatible: "nxp,lpc3220-slc"
> -- reg: Address and size of the controller
> -- nand-on-flash-bbt: Use bad block table on flash
> -- gpios: GPIO specification for NAND write protect
> -
> -The following required properties are very controller specific. See the LPC32xx
> -User Manual:
> -- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
> -- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
> -(The following values are specified in Hz, to make them independent of actual
> -clock speed:)
> -- nxp,wwidth: Write pulse width (W_WIDTH)
> -- nxp,whold: Write hold time (W_HOLD)
> -- nxp,wsetup: Write setup time (W_SETUP)
> -- nxp,rwidth: Read pulse width (R_WIDTH)
> -- nxp,rhold: Read hold time (R_HOLD)
> -- nxp,rsetup: Read setup time (R_SETUP)
> -
> -Optional subnodes:
> -- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml
> -
> -Example:
> -
> -	slc: flash@20020000 {
> -		compatible = "nxp,lpc3220-slc";
> -		reg = <0x20020000 0x1000>;
> -		#address-cells = <1>;
> -		#size-cells = <1>;
> -
> -		nxp,wdr-clks = <14>;
> -		nxp,wwidth = <40000000>;
> -		nxp,whold = <100000000>;
> -		nxp,wsetup = <100000000>;
> -		nxp,rdr-clks = <14>;
> -		nxp,rwidth = <40000000>;
> -		nxp,rhold = <66666666>;
> -		nxp,rsetup = <100000000>;
> -		nand-on-flash-bbt;
> -		gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
> -
> -		mtd0@00000000 {
> -			label = "phy3250-boot";
> -			reg = <0x00000000 0x00064000>;
> -			read-only;
> -		};
> -
> -		...
> -
> -	};
> diff --git a/Documentation/devicetree/bindings/mtd/nxp,lpc3220-slc.yaml b/Documentation/devicetree/bindings/mtd/nxp,lpc3220-slc.yaml
> new file mode 100644
> index 0000000000000..db9cf4efb2212
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/nxp,lpc3220-slc.yaml
> @@ -0,0 +1,101 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/nxp,lpc3220-slc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP LPC32xx SoC NAND SLC controller
> +
> +maintainers:
> +  - Frank Li <Frank.Li@nxp.com>
> +
> +properties:
> +  compatible:
> +    const: nxp,lpc3220-slc
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  gpios:
> +    maxItems: 1
> +    description:
> +      GPIO specification for NAND write protect
> +
> +  nand-on-flash-bbt: true
> +
> +  partitions:
> +    type: object
> +    $ref: partitions/partition.yaml

That's not right... You want partitions.yaml?

> +    unevaluatedProperties: false
> +
> +  nxp,wdr-clks:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Delay before Ready signal is tested on write (W_RDY)
> +
> +  nxp,rdr-clks:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Delay before Ready signal is tested on read (R_RDY)
> +
> +  nxp,wwidth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Write pulse width (W_WIDTH) in Hz
> +
> +  nxp,whold:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Write hold time (W_HOLD) in Hz
> +
> +  nxp,wsetup:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Write setup time (W_SETUP) in Hz
> +
> +  nxp,rwidth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Read pulse width (R_WIDTH) in Hz
> +
> +  nxp,rhold:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Read hold time (R_HOLD) in Hz
> +
> +  nxp,rsetup:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Read setup time (R_SETUP) in Hz
> +
> +required:
> +  - compatible
> +  - reg
> +  - gpios
> +
> +allOf:
> +  - $ref: nand-controller.yaml
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    nand-controller@20020000 {
> +        compatible = "nxp,lpc3220-slc";
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        reg = <0x20020000 0x1000>;
> +        nxp,wdr-clks = <14>;
> +        nxp,wwidth = <40000000>;
> +        nxp,whold = <100000000>;
> +        nxp,wsetup = <100000000>;
> +        nxp,rdr-clks = <14>;
> +        nxp,rwidth = <40000000>;
> +        nxp,rhold = <66666666>;
> +        nxp,rsetup = <100000000>;
> +        nand-on-flash-bbt;
> +        gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
> +    };
> -- 
> 2.34.1
>