* [PATCH v3 1/3] drm/amd: Decrease message level for legacy-pm, kv-dpm and si-dpm
@ 2025-06-27 14:34 Mario Limonciello
2025-06-27 14:34 ` [PATCH v3 2/3] drm/amd: Change legacy-dpm DRM_*() macros to drm_*() Mario Limonciello
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Mario Limonciello @ 2025-06-27 14:34 UTC (permalink / raw)
To: amd-gfx; +Cc: Mario Limonciello, Alexandre Demers
From: Mario Limonciello <mario.limonciello@amd.com>
legacy-pm, kv-dpm and si-dpm have prints while changing power states
that don't have a level and thus are printed by default. These are
not useful at runtime for most people, so decrease them to debug.
Reported-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4322
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
v3:
* Rename functions to include 'dbg' in the name (Lijo)
---
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 16 ++--
.../gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c | 92 +++++++------------
.../gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h | 7 +-
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 10 +-
4 files changed, 50 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index 34e71727b27d7..5d0b18062b8c1 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -2886,16 +2886,18 @@ kv_dpm_print_power_state(void *handle, void *request_ps)
struct kv_ps *ps = kv_get_ps(rps);
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- amdgpu_dpm_print_class_info(rps->class, rps->class2);
- amdgpu_dpm_print_cap_info(rps->caps);
- printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+ amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2);
+ amdgpu_dpm_dbg_print_cap_info(adev, rps->caps);
+ drm_dbg(adev_to_drm(adev), "vclk: %d, dclk: %d\n",
+ rps->vclk, rps->dclk);
for (i = 0; i < ps->num_levels; i++) {
struct kv_pl *pl = &ps->levels[i];
- printk("\t\tpower level %d sclk: %u vddc: %u\n",
- i, pl->sclk,
- kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
+ drm_dbg(adev_to_drm(adev),
+ "power level %d sclk: %u vddc: %u\n",
+ i, pl->sclk,
+ kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
}
- amdgpu_dpm_print_ps_status(adev, rps);
+ amdgpu_dpm_dbg_print_ps_status(adev, rps);
}
static void kv_dpm_fini(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
index c7518b13e7879..2492d9a31bdfa 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
@@ -47,7 +47,7 @@
#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
-void amdgpu_dpm_print_class_info(u32 class, u32 class2)
+void amdgpu_dpm_dbg_print_class_info(struct amdgpu_device *adev, u32 class, u32 class2)
{
const char *s;
@@ -66,71 +66,45 @@ void amdgpu_dpm_print_class_info(u32 class, u32 class2)
s = "performance";
break;
}
- printk("\tui class: %s\n", s);
- printk("\tinternal class:");
+ drm_dbg(adev_to_drm(adev), "\tui class: %s\n", s);
if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) &&
(class2 == 0))
- pr_cont(" none");
- else {
- if (class & ATOM_PPLIB_CLASSIFICATION_BOOT)
- pr_cont(" boot");
- if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
- pr_cont(" thermal");
- if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
- pr_cont(" limited_pwr");
- if (class & ATOM_PPLIB_CLASSIFICATION_REST)
- pr_cont(" rest");
- if (class & ATOM_PPLIB_CLASSIFICATION_FORCED)
- pr_cont(" forced");
- if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
- pr_cont(" 3d_perf");
- if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE)
- pr_cont(" ovrdrv");
- if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
- pr_cont(" uvd");
- if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW)
- pr_cont(" 3d_low");
- if (class & ATOM_PPLIB_CLASSIFICATION_ACPI)
- pr_cont(" acpi");
- if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
- pr_cont(" uvd_hd2");
- if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
- pr_cont(" uvd_hd");
- if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
- pr_cont(" uvd_sd");
- if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
- pr_cont(" limited_pwr2");
- if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
- pr_cont(" ulv");
- if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
- pr_cont(" uvd_mvc");
- }
- pr_cont("\n");
+ drm_dbg(adev_to_drm(adev), "\tinternal class: none\n");
+ else
+ drm_dbg(adev_to_drm(adev), "\tinternal class: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+ (class & ATOM_PPLIB_CLASSIFICATION_BOOT) ? " boot" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_THERMAL) ? " thermal" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) ? " limited_pwr" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_REST) ? " rest" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_FORCED) ? " forced" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) ? " 3d_perf" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE) ? " ovrdrv" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ? " uvd" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_3DLOW) ? " 3d_low" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_ACPI) ? " acpi" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) ? " uvd_hd2" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) ? " uvd_hd" : "",
+ (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ? " uvd_sd" : "",
+ (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) ? " limited_pwr2" : "",
+ (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) ? " ulv" : "",
+ (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) ? " uvd_mvc" : "");
}
-void amdgpu_dpm_print_cap_info(u32 caps)
+void amdgpu_dpm_dbg_print_cap_info(struct amdgpu_device *adev, u32 caps)
{
- printk("\tcaps:");
- if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
- pr_cont(" single_disp");
- if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK)
- pr_cont(" video");
- if (caps & ATOM_PPLIB_DISALLOW_ON_DC)
- pr_cont(" no_dc");
- pr_cont("\n");
+ drm_dbg(adev_to_drm(adev), "\tcaps: %s%s%s\n",
+ (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) ? " single_disp" : "",
+ (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK) ? " video" : "",
+ (caps & ATOM_PPLIB_DISALLOW_ON_DC) ? " no_dc" : "");
}
-void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
+void amdgpu_dpm_dbg_print_ps_status(struct amdgpu_device *adev,
struct amdgpu_ps *rps)
{
- printk("\tstatus:");
- if (rps == adev->pm.dpm.current_ps)
- pr_cont(" c");
- if (rps == adev->pm.dpm.requested_ps)
- pr_cont(" r");
- if (rps == adev->pm.dpm.boot_ps)
- pr_cont(" b");
- pr_cont("\n");
+ drm_dbg(adev_to_drm(adev), "\tstatus:%s%s%s\n",
+ rps == adev->pm.dpm.current_ps ? " c" : "",
+ rps == adev->pm.dpm.requested_ps ? " r" : "",
+ rps == adev->pm.dpm.boot_ps ? " b" : "");
}
void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
@@ -943,9 +917,9 @@ static int amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
return -EINVAL;
if (amdgpu_dpm == 1 && pp_funcs->print_power_state) {
- printk("switching from power state:\n");
+ drm_dbg(adev_to_drm(adev), "switching from power state\n");
amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
- printk("switching to power state:\n");
+ drm_dbg(adev_to_drm(adev), "switching to power state\n");
amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
}
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h
index 93bd3973330cd..7120eef305092 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h
@@ -23,10 +23,9 @@
#ifndef __LEGACY_DPM_H__
#define __LEGACY_DPM_H__
-void amdgpu_dpm_print_class_info(u32 class, u32 class2);
-void amdgpu_dpm_print_cap_info(u32 caps);
-void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
- struct amdgpu_ps *rps);
+void amdgpu_dpm_dbg_print_class_info(struct amdgpu_device *adev, u32 class, u32 class2);
+void amdgpu_dpm_dbg_print_cap_info(struct amdgpu_device *adev, u32 caps);
+void amdgpu_dpm_dbg_print_ps_status(struct amdgpu_device *adev, struct amdgpu_ps *rps);
int amdgpu_get_platform_caps(struct amdgpu_device *adev);
int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 4c0e976004ba4..52e732be59e36 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -7951,15 +7951,15 @@ static void si_dpm_print_power_state(void *handle,
struct rv7xx_pl *pl;
int i;
- amdgpu_dpm_print_class_info(rps->class, rps->class2);
- amdgpu_dpm_print_cap_info(rps->caps);
- DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+ amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2);
+ amdgpu_dpm_dbg_print_cap_info(adev, rps->caps);
+ drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
for (i = 0; i < ps->performance_level_count; i++) {
pl = &ps->performance_levels[i];
- DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
+ drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
}
- amdgpu_dpm_print_ps_status(adev, rps);
+ amdgpu_dpm_dbg_print_ps_status(adev, rps);
}
static int si_dpm_early_init(struct amdgpu_ip_block *ip_block)
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 2/3] drm/amd: Change legacy-dpm DRM_*() macros to drm_*()
2025-06-27 14:34 [PATCH v3 1/3] drm/amd: Decrease message level for legacy-pm, kv-dpm and si-dpm Mario Limonciello
@ 2025-06-27 14:34 ` Mario Limonciello
2025-06-27 14:34 ` [PATCH v3 3/3] drm/amd: Change kv-dpm " Mario Limonciello
2025-06-27 14:56 ` [PATCH v3 1/3] drm/amd: Decrease message level for legacy-pm, kv-dpm and si-dpm Lazar, Lijo
2 siblings, 0 replies; 5+ messages in thread
From: Mario Limonciello @ 2025-06-27 14:34 UTC (permalink / raw)
To: amd-gfx; +Cc: Mario Limonciello, Lijo Lazar, Alexandre Demers
From: Mario Limonciello <mario.limonciello@amd.com>
drm_*() macros can show the device a message came from.
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Cc: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
.../gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c | 26 +++++++++----------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
index 2492d9a31bdfa..ea3ace882a10a 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
@@ -673,64 +673,64 @@ void amdgpu_add_thermal_controller(struct amdgpu_device *adev)
adev->pm.fan_max_rpm = controller->ucFanMaxRPM;
}
if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
- DRM_INFO("Internal thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "Internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
- DRM_INFO("Internal thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "Internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_RV770;
} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
- DRM_INFO("Internal thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "Internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
- DRM_INFO("Internal thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "Internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
- DRM_INFO("Internal thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "Internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_NI;
} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
- DRM_INFO("Internal thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "Internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_SI;
} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
- DRM_INFO("Internal thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "Internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_CI;
} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
- DRM_INFO("Internal thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "Internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_KV;
} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
- DRM_INFO("External GPIO thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "External GPIO thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
} else if (controller->ucType ==
ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
- DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "ADT7473 with internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
} else if (controller->ucType ==
ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
- DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
+ drm_info(adev_to_drm(adev), "EMC2103 with internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
adev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
} else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
- DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
+ drm_info(adev_to_drm(adev), "Possible %s thermal controller at 0x%02x %s fan control\n",
pp_lib_thermal_controller_names[controller->ucType],
controller->ucI2cAddress >> 1,
(controller->ucFanParameters &
@@ -746,7 +746,7 @@ void amdgpu_add_thermal_controller(struct amdgpu_device *adev)
i2c_new_client_device(&adev->pm.i2c_bus->adapter, &info);
}
} else {
- DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
+ drm_info(adev_to_drm(adev), "Unknown thermal controller type %d at 0x%02x %s fan control\n",
controller->ucType,
controller->ucI2cAddress >> 1,
(controller->ucFanParameters &
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 3/3] drm/amd: Change kv-dpm DRM_*() macros to drm_*()
2025-06-27 14:34 [PATCH v3 1/3] drm/amd: Decrease message level for legacy-pm, kv-dpm and si-dpm Mario Limonciello
2025-06-27 14:34 ` [PATCH v3 2/3] drm/amd: Change legacy-dpm DRM_*() macros to drm_*() Mario Limonciello
@ 2025-06-27 14:34 ` Mario Limonciello
2025-06-27 14:44 ` Alex Deucher
2025-06-27 14:56 ` [PATCH v3 1/3] drm/amd: Decrease message level for legacy-pm, kv-dpm and si-dpm Lazar, Lijo
2 siblings, 1 reply; 5+ messages in thread
From: Mario Limonciello @ 2025-06-27 14:34 UTC (permalink / raw)
To: amd-gfx; +Cc: Mario Limonciello, Lijo Lazar, Alexandre Demers
From: Mario Limonciello <mario.limonciello@amd.com>
drm_*() macros can show the device a message came from.
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Cc: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 56 +++++++++++-----------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index 5d0b18062b8c1..307ebf7e32267 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -1242,7 +1242,7 @@ static void kv_dpm_enable_bapm(void *handle, bool enable)
if (pi->bapm_enable) {
ret = amdgpu_kv_smc_bapm_enable(adev, enable);
if (ret)
- DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
+ drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n");
}
}
@@ -1266,40 +1266,40 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
ret = kv_process_firmware_header(adev);
if (ret) {
- DRM_ERROR("kv_process_firmware_header failed\n");
+ drm_err(adev_to_drm(adev), "kv_process_firmware_header failed\n");
return ret;
}
kv_init_fps_limits(adev);
kv_init_graphics_levels(adev);
ret = kv_program_bootup_state(adev);
if (ret) {
- DRM_ERROR("kv_program_bootup_state failed\n");
+ drm_err(adev_to_drm(adev), "kv_program_bootup_state failed\n");
return ret;
}
kv_calculate_dfs_bypass_settings(adev);
ret = kv_upload_dpm_settings(adev);
if (ret) {
- DRM_ERROR("kv_upload_dpm_settings failed\n");
+ drm_err(adev_to_drm(adev), "kv_upload_dpm_settings failed\n");
return ret;
}
ret = kv_populate_uvd_table(adev);
if (ret) {
- DRM_ERROR("kv_populate_uvd_table failed\n");
+ drm_err(adev_to_drm(adev), "kv_populate_uvd_table failed\n");
return ret;
}
ret = kv_populate_vce_table(adev);
if (ret) {
- DRM_ERROR("kv_populate_vce_table failed\n");
+ drm_err(adev_to_drm(adev), "kv_populate_vce_table failed\n");
return ret;
}
ret = kv_populate_samu_table(adev);
if (ret) {
- DRM_ERROR("kv_populate_samu_table failed\n");
+ drm_err(adev_to_drm(adev), "kv_populate_samu_table failed\n");
return ret;
}
ret = kv_populate_acp_table(adev);
if (ret) {
- DRM_ERROR("kv_populate_acp_table failed\n");
+ drm_err(adev_to_drm(adev), "kv_populate_acp_table failed\n");
return ret;
}
kv_program_vc(adev);
@@ -1310,39 +1310,39 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
if (pi->enable_auto_thermal_throttling) {
ret = kv_enable_auto_thermal_throttling(adev);
if (ret) {
- DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
+ drm_err(adev_to_drm(adev), "kv_enable_auto_thermal_throttling failed\n");
return ret;
}
}
ret = kv_enable_dpm_voltage_scaling(adev);
if (ret) {
- DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
+ drm_err(adev_to_drm(adev), "kv_enable_dpm_voltage_scaling failed\n");
return ret;
}
ret = kv_set_dpm_interval(adev);
if (ret) {
- DRM_ERROR("kv_set_dpm_interval failed\n");
+ drm_err(adev_to_drm(adev), "kv_set_dpm_interval failed\n");
return ret;
}
ret = kv_set_dpm_boot_state(adev);
if (ret) {
- DRM_ERROR("kv_set_dpm_boot_state failed\n");
+ drm_err(adev_to_drm(adev), "kv_set_dpm_boot_state failed\n");
return ret;
}
ret = kv_enable_ulv(adev, true);
if (ret) {
- DRM_ERROR("kv_enable_ulv failed\n");
+ drm_err(adev_to_drm(adev), "kv_enable_ulv failed\n");
return ret;
}
kv_start_dpm(adev);
ret = kv_enable_didt(adev, true);
if (ret) {
- DRM_ERROR("kv_enable_didt failed\n");
+ drm_err(adev_to_drm(adev), "kv_enable_didt failed\n");
return ret;
}
ret = kv_enable_smc_cac(adev, true);
if (ret) {
- DRM_ERROR("kv_enable_smc_cac failed\n");
+ drm_err(adev_to_drm(adev), "kv_enable_smc_cac failed\n");
return ret;
}
@@ -1350,7 +1350,7 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
ret = amdgpu_kv_smc_bapm_enable(adev, false);
if (ret) {
- DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
+ drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n");
return ret;
}
@@ -1358,7 +1358,7 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
kv_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
if (ret) {
- DRM_ERROR("kv_set_thermal_temperature_range failed\n");
+ drm_err(adev_to_drm(adev), "kv_set_thermal_temperature_range failed\n");
return ret;
}
amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
@@ -1382,7 +1382,7 @@ static void kv_dpm_disable(struct amdgpu_device *adev)
err = amdgpu_kv_smc_bapm_enable(adev, false);
if (err)
- DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
+ drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n");
if (adev->asic_type == CHIP_MULLINS)
kv_enable_nb_dpm(adev, false);
@@ -1920,7 +1920,7 @@ static int kv_dpm_set_power_state(void *handle)
if (pi->bapm_enable) {
ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power);
if (ret) {
- DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
+ drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n");
return ret;
}
}
@@ -1931,7 +1931,7 @@ static int kv_dpm_set_power_state(void *handle)
kv_update_dfs_bypass_settings(adev, new_ps);
ret = kv_calculate_ds_divider(adev);
if (ret) {
- DRM_ERROR("kv_calculate_ds_divider failed\n");
+ drm_err(adev_to_drm(adev), "kv_calculate_ds_divider failed\n");
return ret;
}
kv_calculate_nbps_level_settings(adev);
@@ -1947,7 +1947,7 @@ static int kv_dpm_set_power_state(void *handle)
ret = kv_update_vce_dpm(adev, new_ps, old_ps);
if (ret) {
- DRM_ERROR("kv_update_vce_dpm failed\n");
+ drm_err(adev_to_drm(adev), "kv_update_vce_dpm failed\n");
return ret;
}
kv_update_sclk_t(adev);
@@ -1960,7 +1960,7 @@ static int kv_dpm_set_power_state(void *handle)
kv_update_dfs_bypass_settings(adev, new_ps);
ret = kv_calculate_ds_divider(adev);
if (ret) {
- DRM_ERROR("kv_calculate_ds_divider failed\n");
+ drm_err(adev_to_drm(adev), "kv_calculate_ds_divider failed\n");
return ret;
}
kv_calculate_nbps_level_settings(adev);
@@ -1972,7 +1972,7 @@ static int kv_dpm_set_power_state(void *handle)
kv_set_enabled_levels(adev);
ret = kv_update_vce_dpm(adev, new_ps, old_ps);
if (ret) {
- DRM_ERROR("kv_update_vce_dpm failed\n");
+ drm_err(adev_to_drm(adev), "kv_update_vce_dpm failed\n");
return ret;
}
kv_update_acp_boot_level(adev);
@@ -2521,7 +2521,7 @@ static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
if (high_temp > max_temp)
high_temp = max_temp;
if (high_temp < low_temp) {
- DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
+ drm_err(adev_to_drm(adev), "invalid thermal range: %d - %d\n", low_temp, high_temp);
return -EINVAL;
}
@@ -2563,7 +2563,7 @@ static int kv_parse_sys_info_table(struct amdgpu_device *adev)
data_offset);
if (crev != 8) {
- DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
+ drm_err(adev_to_drm(adev), "Unsupported IGP table: %d %d\n", frev, crev);
return -EINVAL;
}
pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
@@ -2579,7 +2579,7 @@ static int kv_parse_sys_info_table(struct amdgpu_device *adev)
else
pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
- DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
+ drm_err(adev_to_drm(adev), "The htcTmpLmt should be larger than htcHystLmt.\n");
}
if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
@@ -3015,13 +3015,13 @@ static int kv_dpm_sw_init(struct amdgpu_ip_block *ip_block)
adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
if (amdgpu_dpm == 1)
amdgpu_pm_print_power_states(adev);
- DRM_INFO("amdgpu: dpm initialized\n");
+ drm_info(adev_to_drm(adev), "dpm initialized\n");
return 0;
dpm_failed:
kv_dpm_fini(adev);
- DRM_ERROR("amdgpu: dpm initialization failed\n");
+ drm_err(adev_to_drm(adev), "dpm initialization failed: %d\n", ret);
return ret;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 3/3] drm/amd: Change kv-dpm DRM_*() macros to drm_*()
2025-06-27 14:34 ` [PATCH v3 3/3] drm/amd: Change kv-dpm " Mario Limonciello
@ 2025-06-27 14:44 ` Alex Deucher
0 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2025-06-27 14:44 UTC (permalink / raw)
To: Mario Limonciello
Cc: amd-gfx, Mario Limonciello, Lijo Lazar, Alexandre Demers
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
On Fri, Jun 27, 2025 at 10:43 AM Mario Limonciello <superm1@kernel.org> wrote:
>
> From: Mario Limonciello <mario.limonciello@amd.com>
>
> drm_*() macros can show the device a message came from.
>
> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
> Cc: Alexandre Demers <alexandre.f.demers@gmail.com>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 56 +++++++++++-----------
> 1 file changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> index 5d0b18062b8c1..307ebf7e32267 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> @@ -1242,7 +1242,7 @@ static void kv_dpm_enable_bapm(void *handle, bool enable)
> if (pi->bapm_enable) {
> ret = amdgpu_kv_smc_bapm_enable(adev, enable);
> if (ret)
> - DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
> + drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n");
> }
> }
>
> @@ -1266,40 +1266,40 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
>
> ret = kv_process_firmware_header(adev);
> if (ret) {
> - DRM_ERROR("kv_process_firmware_header failed\n");
> + drm_err(adev_to_drm(adev), "kv_process_firmware_header failed\n");
> return ret;
> }
> kv_init_fps_limits(adev);
> kv_init_graphics_levels(adev);
> ret = kv_program_bootup_state(adev);
> if (ret) {
> - DRM_ERROR("kv_program_bootup_state failed\n");
> + drm_err(adev_to_drm(adev), "kv_program_bootup_state failed\n");
> return ret;
> }
> kv_calculate_dfs_bypass_settings(adev);
> ret = kv_upload_dpm_settings(adev);
> if (ret) {
> - DRM_ERROR("kv_upload_dpm_settings failed\n");
> + drm_err(adev_to_drm(adev), "kv_upload_dpm_settings failed\n");
> return ret;
> }
> ret = kv_populate_uvd_table(adev);
> if (ret) {
> - DRM_ERROR("kv_populate_uvd_table failed\n");
> + drm_err(adev_to_drm(adev), "kv_populate_uvd_table failed\n");
> return ret;
> }
> ret = kv_populate_vce_table(adev);
> if (ret) {
> - DRM_ERROR("kv_populate_vce_table failed\n");
> + drm_err(adev_to_drm(adev), "kv_populate_vce_table failed\n");
> return ret;
> }
> ret = kv_populate_samu_table(adev);
> if (ret) {
> - DRM_ERROR("kv_populate_samu_table failed\n");
> + drm_err(adev_to_drm(adev), "kv_populate_samu_table failed\n");
> return ret;
> }
> ret = kv_populate_acp_table(adev);
> if (ret) {
> - DRM_ERROR("kv_populate_acp_table failed\n");
> + drm_err(adev_to_drm(adev), "kv_populate_acp_table failed\n");
> return ret;
> }
> kv_program_vc(adev);
> @@ -1310,39 +1310,39 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
> if (pi->enable_auto_thermal_throttling) {
> ret = kv_enable_auto_thermal_throttling(adev);
> if (ret) {
> - DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
> + drm_err(adev_to_drm(adev), "kv_enable_auto_thermal_throttling failed\n");
> return ret;
> }
> }
> ret = kv_enable_dpm_voltage_scaling(adev);
> if (ret) {
> - DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
> + drm_err(adev_to_drm(adev), "kv_enable_dpm_voltage_scaling failed\n");
> return ret;
> }
> ret = kv_set_dpm_interval(adev);
> if (ret) {
> - DRM_ERROR("kv_set_dpm_interval failed\n");
> + drm_err(adev_to_drm(adev), "kv_set_dpm_interval failed\n");
> return ret;
> }
> ret = kv_set_dpm_boot_state(adev);
> if (ret) {
> - DRM_ERROR("kv_set_dpm_boot_state failed\n");
> + drm_err(adev_to_drm(adev), "kv_set_dpm_boot_state failed\n");
> return ret;
> }
> ret = kv_enable_ulv(adev, true);
> if (ret) {
> - DRM_ERROR("kv_enable_ulv failed\n");
> + drm_err(adev_to_drm(adev), "kv_enable_ulv failed\n");
> return ret;
> }
> kv_start_dpm(adev);
> ret = kv_enable_didt(adev, true);
> if (ret) {
> - DRM_ERROR("kv_enable_didt failed\n");
> + drm_err(adev_to_drm(adev), "kv_enable_didt failed\n");
> return ret;
> }
> ret = kv_enable_smc_cac(adev, true);
> if (ret) {
> - DRM_ERROR("kv_enable_smc_cac failed\n");
> + drm_err(adev_to_drm(adev), "kv_enable_smc_cac failed\n");
> return ret;
> }
>
> @@ -1350,7 +1350,7 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
>
> ret = amdgpu_kv_smc_bapm_enable(adev, false);
> if (ret) {
> - DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
> + drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n");
> return ret;
> }
>
> @@ -1358,7 +1358,7 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
> kv_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
> ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
> if (ret) {
> - DRM_ERROR("kv_set_thermal_temperature_range failed\n");
> + drm_err(adev_to_drm(adev), "kv_set_thermal_temperature_range failed\n");
> return ret;
> }
> amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
> @@ -1382,7 +1382,7 @@ static void kv_dpm_disable(struct amdgpu_device *adev)
>
> err = amdgpu_kv_smc_bapm_enable(adev, false);
> if (err)
> - DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
> + drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n");
>
> if (adev->asic_type == CHIP_MULLINS)
> kv_enable_nb_dpm(adev, false);
> @@ -1920,7 +1920,7 @@ static int kv_dpm_set_power_state(void *handle)
> if (pi->bapm_enable) {
> ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power);
> if (ret) {
> - DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
> + drm_err(adev_to_drm(adev), "amdgpu_kv_smc_bapm_enable failed\n");
> return ret;
> }
> }
> @@ -1931,7 +1931,7 @@ static int kv_dpm_set_power_state(void *handle)
> kv_update_dfs_bypass_settings(adev, new_ps);
> ret = kv_calculate_ds_divider(adev);
> if (ret) {
> - DRM_ERROR("kv_calculate_ds_divider failed\n");
> + drm_err(adev_to_drm(adev), "kv_calculate_ds_divider failed\n");
> return ret;
> }
> kv_calculate_nbps_level_settings(adev);
> @@ -1947,7 +1947,7 @@ static int kv_dpm_set_power_state(void *handle)
>
> ret = kv_update_vce_dpm(adev, new_ps, old_ps);
> if (ret) {
> - DRM_ERROR("kv_update_vce_dpm failed\n");
> + drm_err(adev_to_drm(adev), "kv_update_vce_dpm failed\n");
> return ret;
> }
> kv_update_sclk_t(adev);
> @@ -1960,7 +1960,7 @@ static int kv_dpm_set_power_state(void *handle)
> kv_update_dfs_bypass_settings(adev, new_ps);
> ret = kv_calculate_ds_divider(adev);
> if (ret) {
> - DRM_ERROR("kv_calculate_ds_divider failed\n");
> + drm_err(adev_to_drm(adev), "kv_calculate_ds_divider failed\n");
> return ret;
> }
> kv_calculate_nbps_level_settings(adev);
> @@ -1972,7 +1972,7 @@ static int kv_dpm_set_power_state(void *handle)
> kv_set_enabled_levels(adev);
> ret = kv_update_vce_dpm(adev, new_ps, old_ps);
> if (ret) {
> - DRM_ERROR("kv_update_vce_dpm failed\n");
> + drm_err(adev_to_drm(adev), "kv_update_vce_dpm failed\n");
> return ret;
> }
> kv_update_acp_boot_level(adev);
> @@ -2521,7 +2521,7 @@ static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
> if (high_temp > max_temp)
> high_temp = max_temp;
> if (high_temp < low_temp) {
> - DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
> + drm_err(adev_to_drm(adev), "invalid thermal range: %d - %d\n", low_temp, high_temp);
> return -EINVAL;
> }
>
> @@ -2563,7 +2563,7 @@ static int kv_parse_sys_info_table(struct amdgpu_device *adev)
> data_offset);
>
> if (crev != 8) {
> - DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
> + drm_err(adev_to_drm(adev), "Unsupported IGP table: %d %d\n", frev, crev);
> return -EINVAL;
> }
> pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
> @@ -2579,7 +2579,7 @@ static int kv_parse_sys_info_table(struct amdgpu_device *adev)
> else
> pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
> if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
> - DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
> + drm_err(adev_to_drm(adev), "The htcTmpLmt should be larger than htcHystLmt.\n");
> }
>
> if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
> @@ -3015,13 +3015,13 @@ static int kv_dpm_sw_init(struct amdgpu_ip_block *ip_block)
> adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
> if (amdgpu_dpm == 1)
> amdgpu_pm_print_power_states(adev);
> - DRM_INFO("amdgpu: dpm initialized\n");
> + drm_info(adev_to_drm(adev), "dpm initialized\n");
>
> return 0;
>
> dpm_failed:
> kv_dpm_fini(adev);
> - DRM_ERROR("amdgpu: dpm initialization failed\n");
> + drm_err(adev_to_drm(adev), "dpm initialization failed: %d\n", ret);
> return ret;
> }
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 1/3] drm/amd: Decrease message level for legacy-pm, kv-dpm and si-dpm
2025-06-27 14:34 [PATCH v3 1/3] drm/amd: Decrease message level for legacy-pm, kv-dpm and si-dpm Mario Limonciello
2025-06-27 14:34 ` [PATCH v3 2/3] drm/amd: Change legacy-dpm DRM_*() macros to drm_*() Mario Limonciello
2025-06-27 14:34 ` [PATCH v3 3/3] drm/amd: Change kv-dpm " Mario Limonciello
@ 2025-06-27 14:56 ` Lazar, Lijo
2 siblings, 0 replies; 5+ messages in thread
From: Lazar, Lijo @ 2025-06-27 14:56 UTC (permalink / raw)
To: Mario Limonciello, amd-gfx; +Cc: Mario Limonciello, Alexandre Demers
On 6/27/2025 8:04 PM, Mario Limonciello wrote:
> From: Mario Limonciello <mario.limonciello@amd.com>
>
> legacy-pm, kv-dpm and si-dpm have prints while changing power states
> that don't have a level and thus are printed by default. These are
> not useful at runtime for most people, so decrease them to debug.
>
> Reported-by: Alexandre Demers <alexandre.f.demers@gmail.com>
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4322
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Thanks,
Lijo
> ---
> v3:
> * Rename functions to include 'dbg' in the name (Lijo)
> ---
> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 16 ++--
> .../gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c | 92 +++++++------------
> .../gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h | 7 +-
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 10 +-
> 4 files changed, 50 insertions(+), 75 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> index 34e71727b27d7..5d0b18062b8c1 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> @@ -2886,16 +2886,18 @@ kv_dpm_print_power_state(void *handle, void *request_ps)
> struct kv_ps *ps = kv_get_ps(rps);
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - amdgpu_dpm_print_class_info(rps->class, rps->class2);
> - amdgpu_dpm_print_cap_info(rps->caps);
> - printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
> + amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2);
> + amdgpu_dpm_dbg_print_cap_info(adev, rps->caps);
> + drm_dbg(adev_to_drm(adev), "vclk: %d, dclk: %d\n",
> + rps->vclk, rps->dclk);
> for (i = 0; i < ps->num_levels; i++) {
> struct kv_pl *pl = &ps->levels[i];
> - printk("\t\tpower level %d sclk: %u vddc: %u\n",
> - i, pl->sclk,
> - kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
> + drm_dbg(adev_to_drm(adev),
> + "power level %d sclk: %u vddc: %u\n",
> + i, pl->sclk,
> + kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
> }
> - amdgpu_dpm_print_ps_status(adev, rps);
> + amdgpu_dpm_dbg_print_ps_status(adev, rps);
> }
>
> static void kv_dpm_fini(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
> index c7518b13e7879..2492d9a31bdfa 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
> @@ -47,7 +47,7 @@
> #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
> ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
>
> -void amdgpu_dpm_print_class_info(u32 class, u32 class2)
> +void amdgpu_dpm_dbg_print_class_info(struct amdgpu_device *adev, u32 class, u32 class2)
> {
> const char *s;
>
> @@ -66,71 +66,45 @@ void amdgpu_dpm_print_class_info(u32 class, u32 class2)
> s = "performance";
> break;
> }
> - printk("\tui class: %s\n", s);
> - printk("\tinternal class:");
> + drm_dbg(adev_to_drm(adev), "\tui class: %s\n", s);
> if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) &&
> (class2 == 0))
> - pr_cont(" none");
> - else {
> - if (class & ATOM_PPLIB_CLASSIFICATION_BOOT)
> - pr_cont(" boot");
> - if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
> - pr_cont(" thermal");
> - if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
> - pr_cont(" limited_pwr");
> - if (class & ATOM_PPLIB_CLASSIFICATION_REST)
> - pr_cont(" rest");
> - if (class & ATOM_PPLIB_CLASSIFICATION_FORCED)
> - pr_cont(" forced");
> - if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
> - pr_cont(" 3d_perf");
> - if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE)
> - pr_cont(" ovrdrv");
> - if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
> - pr_cont(" uvd");
> - if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW)
> - pr_cont(" 3d_low");
> - if (class & ATOM_PPLIB_CLASSIFICATION_ACPI)
> - pr_cont(" acpi");
> - if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
> - pr_cont(" uvd_hd2");
> - if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
> - pr_cont(" uvd_hd");
> - if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
> - pr_cont(" uvd_sd");
> - if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
> - pr_cont(" limited_pwr2");
> - if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
> - pr_cont(" ulv");
> - if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
> - pr_cont(" uvd_mvc");
> - }
> - pr_cont("\n");
> + drm_dbg(adev_to_drm(adev), "\tinternal class: none\n");
> + else
> + drm_dbg(adev_to_drm(adev), "\tinternal class: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
> + (class & ATOM_PPLIB_CLASSIFICATION_BOOT) ? " boot" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_THERMAL) ? " thermal" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) ? " limited_pwr" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_REST) ? " rest" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_FORCED) ? " forced" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) ? " 3d_perf" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE) ? " ovrdrv" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ? " uvd" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_3DLOW) ? " 3d_low" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_ACPI) ? " acpi" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) ? " uvd_hd2" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) ? " uvd_hd" : "",
> + (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ? " uvd_sd" : "",
> + (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) ? " limited_pwr2" : "",
> + (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) ? " ulv" : "",
> + (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) ? " uvd_mvc" : "");
> }
>
> -void amdgpu_dpm_print_cap_info(u32 caps)
> +void amdgpu_dpm_dbg_print_cap_info(struct amdgpu_device *adev, u32 caps)
> {
> - printk("\tcaps:");
> - if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
> - pr_cont(" single_disp");
> - if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK)
> - pr_cont(" video");
> - if (caps & ATOM_PPLIB_DISALLOW_ON_DC)
> - pr_cont(" no_dc");
> - pr_cont("\n");
> + drm_dbg(adev_to_drm(adev), "\tcaps: %s%s%s\n",
> + (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) ? " single_disp" : "",
> + (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK) ? " video" : "",
> + (caps & ATOM_PPLIB_DISALLOW_ON_DC) ? " no_dc" : "");
> }
>
> -void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
> +void amdgpu_dpm_dbg_print_ps_status(struct amdgpu_device *adev,
> struct amdgpu_ps *rps)
> {
> - printk("\tstatus:");
> - if (rps == adev->pm.dpm.current_ps)
> - pr_cont(" c");
> - if (rps == adev->pm.dpm.requested_ps)
> - pr_cont(" r");
> - if (rps == adev->pm.dpm.boot_ps)
> - pr_cont(" b");
> - pr_cont("\n");
> + drm_dbg(adev_to_drm(adev), "\tstatus:%s%s%s\n",
> + rps == adev->pm.dpm.current_ps ? " c" : "",
> + rps == adev->pm.dpm.requested_ps ? " r" : "",
> + rps == adev->pm.dpm.boot_ps ? " b" : "");
> }
>
> void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
> @@ -943,9 +917,9 @@ static int amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
> return -EINVAL;
>
> if (amdgpu_dpm == 1 && pp_funcs->print_power_state) {
> - printk("switching from power state:\n");
> + drm_dbg(adev_to_drm(adev), "switching from power state\n");
> amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
> - printk("switching to power state:\n");
> + drm_dbg(adev_to_drm(adev), "switching to power state\n");
> amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
> }
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h
> index 93bd3973330cd..7120eef305092 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h
> @@ -23,10 +23,9 @@
> #ifndef __LEGACY_DPM_H__
> #define __LEGACY_DPM_H__
>
> -void amdgpu_dpm_print_class_info(u32 class, u32 class2);
> -void amdgpu_dpm_print_cap_info(u32 caps);
> -void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
> - struct amdgpu_ps *rps);
> +void amdgpu_dpm_dbg_print_class_info(struct amdgpu_device *adev, u32 class, u32 class2);
> +void amdgpu_dpm_dbg_print_cap_info(struct amdgpu_device *adev, u32 caps);
> +void amdgpu_dpm_dbg_print_ps_status(struct amdgpu_device *adev, struct amdgpu_ps *rps);
> int amdgpu_get_platform_caps(struct amdgpu_device *adev);
> int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
> void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index 4c0e976004ba4..52e732be59e36 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -7951,15 +7951,15 @@ static void si_dpm_print_power_state(void *handle,
> struct rv7xx_pl *pl;
> int i;
>
> - amdgpu_dpm_print_class_info(rps->class, rps->class2);
> - amdgpu_dpm_print_cap_info(rps->caps);
> - DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
> + amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2);
> + amdgpu_dpm_dbg_print_cap_info(adev, rps->caps);
> + drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
> for (i = 0; i < ps->performance_level_count; i++) {
> pl = &ps->performance_levels[i];
> - DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
> + drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
> i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
> }
> - amdgpu_dpm_print_ps_status(adev, rps);
> + amdgpu_dpm_dbg_print_ps_status(adev, rps);
> }
>
> static int si_dpm_early_init(struct amdgpu_ip_block *ip_block)
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-06-27 14:56 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-06-27 14:34 [PATCH v3 1/3] drm/amd: Decrease message level for legacy-pm, kv-dpm and si-dpm Mario Limonciello
2025-06-27 14:34 ` [PATCH v3 2/3] drm/amd: Change legacy-dpm DRM_*() macros to drm_*() Mario Limonciello
2025-06-27 14:34 ` [PATCH v3 3/3] drm/amd: Change kv-dpm " Mario Limonciello
2025-06-27 14:44 ` Alex Deucher
2025-06-27 14:56 ` [PATCH v3 1/3] drm/amd: Decrease message level for legacy-pm, kv-dpm and si-dpm Lazar, Lijo
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