From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Eric Auger <eric.auger@redhat.com>
Cc: qemu-devel@nongnu.org, "Fan Ni" <fan.ni@samsung.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
mst@redhat.com, "Zhijian Li" <lizhijian@fujitsu.com>,
"Itaru Kitayama" <itaru.kitayama@linux.dev>,
linuxarm@huawei.com, linux-cxl@vger.kernel.org,
qemu-arm@nongnu.org,
"Yuquan Wang" <wangyuquan1236@phytium.com.cn>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [PATCH qemu v16 3/5] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl
Date: Tue, 1 Jul 2025 15:41:10 +0100 [thread overview]
Message-ID: <20250701154110.00007675@huawei.com> (raw)
In-Reply-To: <4ceea721-b633-499e-9fcd-735990ee0704@redhat.com>
On Tue, 1 Jul 2025 15:26:26 +0200
Eric Auger <eric.auger@redhat.com> wrote:
> Hi Jonathan,
>
> On 6/25/25 6:19 PM, Jonathan Cameron via wrote:
> > Code based on i386/pc enablement.
> > The memory layout places space for 16 host bridge register regions after
> > the GIC_REDIST2 in the extended memmap. This is a hole in the current
> > map so adding them here has no impact on placement of other memory regions
> > (tested with enough CPUs for GIC_REDIST2 to be in use.)
>
> Doesn't it depend on the init RAM size setting.
> if the init RAM top + REDIST2 aligns to a 256MB boundary (size of the
> PCI ECAM) aren't you likely to have no hole?
Hi Eric,
Is that possible? I think the device_memory_base being force to align
to a 1 GiB means that never happens. That seems to occur even
if there is no device_memory.
device_memory_base =
ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
/* Base address of the high IO region */
memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
//So here we are GiB aligned.
...
if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
}
//That's 256 GiB in or leave it alone as more than that but GiB aligned.
/* We know for sure that at least the memory fits in the PA space */
vms->highest_gpa = memtop - 1;
virt_set_high_memmap(vms, base, pa_bits);
So I think I'm fine. I should call out that REDIST2 is GiB
aligned though in this patch description.
>
>
> >
> > The CFMWs are placed above the extended memmap. Note the confusing
> > existing variable highest_gpa is the highest_gpa that has been allocated
> > at a particular point in setting up the memory map.
> what kind of improvement would you foresee wrt highest_gpa?
This was mostly a response to Peter expressed that he was expecting
highest_gpa to reflect the limit, not the highest yet seen.
I'm not sure how to resolve that without having awkward naming
like highest_gpa_sofar. There are existing comments where it is updated
so I'm not thinking we need to change anything for this.
Thanks for taking a look,
Jonathan
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Eric Auger <eric.auger@redhat.com>
Cc: qemu-devel@nongnu.org, "Fan Ni" <fan.ni@samsung.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
mst@redhat.com, "Zhijian Li" <lizhijian@fujitsu.com>,
"Itaru Kitayama" <itaru.kitayama@linux.dev>,
linuxarm@huawei.com, linux-cxl@vger.kernel.org,
qemu-arm@nongnu.org,
"Yuquan Wang" <wangyuquan1236@phytium.com.cn>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [PATCH qemu v16 3/5] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl
Date: Tue, 1 Jul 2025 15:41:10 +0100 [thread overview]
Message-ID: <20250701154110.00007675@huawei.com> (raw)
In-Reply-To: <4ceea721-b633-499e-9fcd-735990ee0704@redhat.com>
On Tue, 1 Jul 2025 15:26:26 +0200
Eric Auger <eric.auger@redhat.com> wrote:
> Hi Jonathan,
>
> On 6/25/25 6:19 PM, Jonathan Cameron via wrote:
> > Code based on i386/pc enablement.
> > The memory layout places space for 16 host bridge register regions after
> > the GIC_REDIST2 in the extended memmap. This is a hole in the current
> > map so adding them here has no impact on placement of other memory regions
> > (tested with enough CPUs for GIC_REDIST2 to be in use.)
>
> Doesn't it depend on the init RAM size setting.
> if the init RAM top + REDIST2 aligns to a 256MB boundary (size of the
> PCI ECAM) aren't you likely to have no hole?
Hi Eric,
Is that possible? I think the device_memory_base being force to align
to a 1 GiB means that never happens. That seems to occur even
if there is no device_memory.
device_memory_base =
ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
/* Base address of the high IO region */
memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
//So here we are GiB aligned.
...
if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
}
//That's 256 GiB in or leave it alone as more than that but GiB aligned.
/* We know for sure that at least the memory fits in the PA space */
vms->highest_gpa = memtop - 1;
virt_set_high_memmap(vms, base, pa_bits);
So I think I'm fine. I should call out that REDIST2 is GiB
aligned though in this patch description.
>
>
> >
> > The CFMWs are placed above the extended memmap. Note the confusing
> > existing variable highest_gpa is the highest_gpa that has been allocated
> > at a particular point in setting up the memory map.
> what kind of improvement would you foresee wrt highest_gpa?
This was mostly a response to Peter expressed that he was expecting
highest_gpa to reflect the limit, not the highest yet seen.
I'm not sure how to resolve that without having awkward naming
like highest_gpa_sofar. There are existing comments where it is updated
so I'm not thinking we need to change anything for this.
Thanks for taking a look,
Jonathan
next prev parent reply other threads:[~2025-07-01 14:41 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-25 16:19 [PATCH qemu v16 0/5] arm/virt: CXL support via pxb_cxl Jonathan Cameron
2025-06-25 16:19 ` Jonathan Cameron via
2025-06-25 16:19 ` [PATCH qemu v16 1/5] hw/cxl-host: Add an index field to CXLFixedMemoryWindow Jonathan Cameron
2025-06-25 16:19 ` Jonathan Cameron via
2025-07-01 15:50 ` Eric Auger
2025-06-25 16:19 ` [PATCH qemu v16 2/5] hw/cxl: Make the CXL fixed memory windows devices Jonathan Cameron
2025-06-25 16:19 ` Jonathan Cameron via
2025-06-25 16:19 ` [PATCH qemu v16 3/5] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2025-06-25 16:19 ` Jonathan Cameron via
2025-07-01 13:26 ` Eric Auger
2025-07-01 14:41 ` Jonathan Cameron [this message]
2025-07-01 14:41 ` Jonathan Cameron via
2025-07-01 15:03 ` Eric Auger
2025-07-01 15:34 ` Eric Auger
2025-07-01 15:52 ` Jonathan Cameron
2025-07-01 15:52 ` Jonathan Cameron via
2025-07-01 16:12 ` Eric Auger
2025-07-01 16:26 ` Jonathan Cameron
2025-07-01 16:26 ` Jonathan Cameron via
2025-06-25 16:19 ` [PATCH qemu v16 4/5] docs/cxl: Add an arm/virt example Jonathan Cameron
2025-06-25 16:19 ` Jonathan Cameron via
2025-07-01 15:42 ` Eric Auger
2025-06-25 16:19 ` [PATCH qemu v16 5/5] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2025-06-25 16:19 ` Jonathan Cameron via
2025-06-26 2:33 ` Itaru Kitayama
2025-07-01 15:47 ` Eric Auger
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