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From: Anup Patel <apatel@ventanamicro.com>
To: "Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Jassi Brar" <jassisinghbrar@gmail.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <brgl@bgdev.pl>,
	"Uwe Kleine-König" <ukleinek@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Alexandre Ghiti <alex@ghiti.fr>, Len Brown <lenb@kernel.org>,
	Sunil V L <sunilvl@ventanamicro.com>,
	Rahul Pathak <rpathak@ventanamicro.com>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	Atish Patra <atish.patra@linux.dev>,
	Andrew Jones <ajones@ventanamicro.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Anup Patel <anup@brainfault.org>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>,
	Atish Patra <atishp@rivosinc.com>
Subject: [PATCH v7 03/24] RISC-V: Add defines for the SBI message proxy extension
Date: Wed,  2 Jul 2025 10:43:24 +0530	[thread overview]
Message-ID: <20250702051345.1460497-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com>

Add defines for the new SBI message proxy extension which is part
of the SBI v3.0 specification.

Reviewed-by: Atish Patra <atishp@rivosinc.com>
Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/sbi.h | 63 ++++++++++++++++++++++++++++++++++++
 include/linux/wordpart.h     |  8 +++++
 2 files changed, 71 insertions(+)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 341e74238aa0..59a7285ff956 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -10,6 +10,7 @@
 #include <linux/types.h>
 #include <linux/cpumask.h>
 #include <linux/jump_label.h>
+#include <linux/wordpart.h>
 
 #ifdef CONFIG_RISCV_SBI
 enum sbi_ext_id {
@@ -36,6 +37,7 @@ enum sbi_ext_id {
 	SBI_EXT_STA = 0x535441,
 	SBI_EXT_NACL = 0x4E41434C,
 	SBI_EXT_FWFT = 0x46574654,
+	SBI_EXT_MPXY = 0x4D505859,
 
 	/* Experimentals extensions must lie within this range */
 	SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -430,6 +432,67 @@ enum sbi_fwft_feature_t {
 
 #define SBI_FWFT_SET_FLAG_LOCK			BIT(0)
 
+enum sbi_ext_mpxy_fid {
+	SBI_EXT_MPXY_GET_SHMEM_SIZE,
+	SBI_EXT_MPXY_SET_SHMEM,
+	SBI_EXT_MPXY_GET_CHANNEL_IDS,
+	SBI_EXT_MPXY_READ_ATTRS,
+	SBI_EXT_MPXY_WRITE_ATTRS,
+	SBI_EXT_MPXY_SEND_MSG_WITH_RESP,
+	SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP,
+	SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS
+};
+
+enum sbi_mpxy_attribute_id {
+	/* Standard channel attributes managed by MPXY framework */
+	SBI_MPXY_ATTR_MSG_PROT_ID		= 0x00000000,
+	SBI_MPXY_ATTR_MSG_PROT_VER		= 0x00000001,
+	SBI_MPXY_ATTR_MSG_MAX_LEN		= 0x00000002,
+	SBI_MPXY_ATTR_MSG_SEND_TIMEOUT		= 0x00000003,
+	SBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT	= 0x00000004,
+	SBI_MPXY_ATTR_CHANNEL_CAPABILITY	= 0x00000005,
+	SBI_MPXY_ATTR_SSE_EVENT_ID		= 0x00000006,
+	SBI_MPXY_ATTR_MSI_CONTROL		= 0x00000007,
+	SBI_MPXY_ATTR_MSI_ADDR_LO		= 0x00000008,
+	SBI_MPXY_ATTR_MSI_ADDR_HI		= 0x00000009,
+	SBI_MPXY_ATTR_MSI_DATA			= 0x0000000A,
+	SBI_MPXY_ATTR_EVENTS_STATE_CONTROL	= 0x0000000B,
+	SBI_MPXY_ATTR_STD_ATTR_MAX_IDX,
+	/*
+	 * Message protocol specific attributes, managed by
+	 * the message protocol specification.
+	 */
+	SBI_MPXY_ATTR_MSGPROTO_ATTR_START	= 0x80000000,
+	SBI_MPXY_ATTR_MSGPROTO_ATTR_END		= 0xffffffff
+};
+
+/* Possible values of MSG_PROT_ID attribute */
+enum sbi_mpxy_msgproto_id {
+	SBI_MPXY_MSGPROTO_RPMI_ID = 0x0
+};
+
+/* RPMI message protocol specific MPXY attributes */
+enum sbi_mpxy_rpmi_attribute_id {
+	SBI_MPXY_RPMI_ATTR_SERVICEGROUP_ID = SBI_MPXY_ATTR_MSGPROTO_ATTR_START,
+	SBI_MPXY_RPMI_ATTR_SERVICEGROUP_VERSION,
+	SBI_MPXY_RPMI_ATTR_IMPL_ID,
+	SBI_MPXY_RPMI_ATTR_IMPL_VERSION,
+	SBI_MPXY_RPMI_ATTR_MAX_ID
+};
+
+/* Encoding of MSG_PROT_VER attribute */
+#define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver)	upper_16_bits(__ver)
+#define SBI_MPXY_MSG_PROT_VER_MINOR(__ver)	lower_16_bits(__ver)
+#define SBI_MPXY_MSG_PROT_MKVER(__maj, __min)	make_u32_from_two_u16(__maj, __min)
+
+/* Capabilities available through CHANNEL_CAPABILITY attribute */
+#define SBI_MPXY_CHAN_CAP_MSI			BIT(0)
+#define SBI_MPXY_CHAN_CAP_SSE			BIT(1)
+#define SBI_MPXY_CHAN_CAP_EVENTS_STATE		BIT(2)
+#define SBI_MPXY_CHAN_CAP_SEND_WITH_RESP	BIT(3)
+#define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP	BIT(4)
+#define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS	BIT(5)
+
 /* SBI spec version fields */
 #define SBI_SPEC_VERSION_DEFAULT	0x1
 #define SBI_SPEC_VERSION_MAJOR_SHIFT	24
diff --git a/include/linux/wordpart.h b/include/linux/wordpart.h
index 5a7b97bb7c95..ed8717730037 100644
--- a/include/linux/wordpart.h
+++ b/include/linux/wordpart.h
@@ -31,6 +31,14 @@
  */
 #define lower_16_bits(n) ((u16)((n) & 0xffff))
 
+/**
+ * make_u32_from_two_u16 - return u32 number by combining
+ * two u16 numbers.
+ * @hi: upper 16 bit number
+ * @lo: lower 16 bit number
+ */
+#define make_u32_from_two_u16(hi, lo)	(((u32)(hi) << 16) | (u32)(lo))
+
 /**
  * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
  * @x: value to repeat
-- 
2.43.0


WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: "Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Jassi Brar" <jassisinghbrar@gmail.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <brgl@bgdev.pl>,
	"Uwe Kleine-König" <ukleinek@kernel.org>
Cc: Anup Patel <apatel@ventanamicro.com>,
	devicetree@vger.kernel.org,
	Andrew Jones <ajones@ventanamicro.com>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Atish Patra <atish.patra@linux.dev>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@rivosinc.com>,
	linux-kernel@vger.kernel.org,
	Samuel Holland <samuel.holland@sifive.com>,
	linux-acpi@vger.kernel.org, Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org, Len Brown <lenb@kernel.org>,
	linux-clk@vger.kernel.org,
	Rahul Pathak <rpathak@ventanamicro.com>
Subject: [PATCH v7 03/24] RISC-V: Add defines for the SBI message proxy extension
Date: Wed,  2 Jul 2025 10:43:24 +0530	[thread overview]
Message-ID: <20250702051345.1460497-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20250702051345.1460497-1-apatel@ventanamicro.com>

Add defines for the new SBI message proxy extension which is part
of the SBI v3.0 specification.

Reviewed-by: Atish Patra <atishp@rivosinc.com>
Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/sbi.h | 63 ++++++++++++++++++++++++++++++++++++
 include/linux/wordpart.h     |  8 +++++
 2 files changed, 71 insertions(+)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 341e74238aa0..59a7285ff956 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -10,6 +10,7 @@
 #include <linux/types.h>
 #include <linux/cpumask.h>
 #include <linux/jump_label.h>
+#include <linux/wordpart.h>
 
 #ifdef CONFIG_RISCV_SBI
 enum sbi_ext_id {
@@ -36,6 +37,7 @@ enum sbi_ext_id {
 	SBI_EXT_STA = 0x535441,
 	SBI_EXT_NACL = 0x4E41434C,
 	SBI_EXT_FWFT = 0x46574654,
+	SBI_EXT_MPXY = 0x4D505859,
 
 	/* Experimentals extensions must lie within this range */
 	SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -430,6 +432,67 @@ enum sbi_fwft_feature_t {
 
 #define SBI_FWFT_SET_FLAG_LOCK			BIT(0)
 
+enum sbi_ext_mpxy_fid {
+	SBI_EXT_MPXY_GET_SHMEM_SIZE,
+	SBI_EXT_MPXY_SET_SHMEM,
+	SBI_EXT_MPXY_GET_CHANNEL_IDS,
+	SBI_EXT_MPXY_READ_ATTRS,
+	SBI_EXT_MPXY_WRITE_ATTRS,
+	SBI_EXT_MPXY_SEND_MSG_WITH_RESP,
+	SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP,
+	SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS
+};
+
+enum sbi_mpxy_attribute_id {
+	/* Standard channel attributes managed by MPXY framework */
+	SBI_MPXY_ATTR_MSG_PROT_ID		= 0x00000000,
+	SBI_MPXY_ATTR_MSG_PROT_VER		= 0x00000001,
+	SBI_MPXY_ATTR_MSG_MAX_LEN		= 0x00000002,
+	SBI_MPXY_ATTR_MSG_SEND_TIMEOUT		= 0x00000003,
+	SBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT	= 0x00000004,
+	SBI_MPXY_ATTR_CHANNEL_CAPABILITY	= 0x00000005,
+	SBI_MPXY_ATTR_SSE_EVENT_ID		= 0x00000006,
+	SBI_MPXY_ATTR_MSI_CONTROL		= 0x00000007,
+	SBI_MPXY_ATTR_MSI_ADDR_LO		= 0x00000008,
+	SBI_MPXY_ATTR_MSI_ADDR_HI		= 0x00000009,
+	SBI_MPXY_ATTR_MSI_DATA			= 0x0000000A,
+	SBI_MPXY_ATTR_EVENTS_STATE_CONTROL	= 0x0000000B,
+	SBI_MPXY_ATTR_STD_ATTR_MAX_IDX,
+	/*
+	 * Message protocol specific attributes, managed by
+	 * the message protocol specification.
+	 */
+	SBI_MPXY_ATTR_MSGPROTO_ATTR_START	= 0x80000000,
+	SBI_MPXY_ATTR_MSGPROTO_ATTR_END		= 0xffffffff
+};
+
+/* Possible values of MSG_PROT_ID attribute */
+enum sbi_mpxy_msgproto_id {
+	SBI_MPXY_MSGPROTO_RPMI_ID = 0x0
+};
+
+/* RPMI message protocol specific MPXY attributes */
+enum sbi_mpxy_rpmi_attribute_id {
+	SBI_MPXY_RPMI_ATTR_SERVICEGROUP_ID = SBI_MPXY_ATTR_MSGPROTO_ATTR_START,
+	SBI_MPXY_RPMI_ATTR_SERVICEGROUP_VERSION,
+	SBI_MPXY_RPMI_ATTR_IMPL_ID,
+	SBI_MPXY_RPMI_ATTR_IMPL_VERSION,
+	SBI_MPXY_RPMI_ATTR_MAX_ID
+};
+
+/* Encoding of MSG_PROT_VER attribute */
+#define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver)	upper_16_bits(__ver)
+#define SBI_MPXY_MSG_PROT_VER_MINOR(__ver)	lower_16_bits(__ver)
+#define SBI_MPXY_MSG_PROT_MKVER(__maj, __min)	make_u32_from_two_u16(__maj, __min)
+
+/* Capabilities available through CHANNEL_CAPABILITY attribute */
+#define SBI_MPXY_CHAN_CAP_MSI			BIT(0)
+#define SBI_MPXY_CHAN_CAP_SSE			BIT(1)
+#define SBI_MPXY_CHAN_CAP_EVENTS_STATE		BIT(2)
+#define SBI_MPXY_CHAN_CAP_SEND_WITH_RESP	BIT(3)
+#define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP	BIT(4)
+#define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS	BIT(5)
+
 /* SBI spec version fields */
 #define SBI_SPEC_VERSION_DEFAULT	0x1
 #define SBI_SPEC_VERSION_MAJOR_SHIFT	24
diff --git a/include/linux/wordpart.h b/include/linux/wordpart.h
index 5a7b97bb7c95..ed8717730037 100644
--- a/include/linux/wordpart.h
+++ b/include/linux/wordpart.h
@@ -31,6 +31,14 @@
  */
 #define lower_16_bits(n) ((u16)((n) & 0xffff))
 
+/**
+ * make_u32_from_two_u16 - return u32 number by combining
+ * two u16 numbers.
+ * @hi: upper 16 bit number
+ * @lo: lower 16 bit number
+ */
+#define make_u32_from_two_u16(hi, lo)	(((u32)(hi) << 16) | (u32)(lo))
+
 /**
  * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
  * @x: value to repeat
-- 
2.43.0


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  parent reply	other threads:[~2025-07-02  5:14 UTC|newest]

Thread overview: 110+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-02  5:13 [PATCH v7 00/24] Linux SBI MPXY and RPMI drivers Anup Patel
2025-07-02  5:13 ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 01/24] dt-bindings: mailbox: Add bindings for RPMI shared memory transport Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 02/24] dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` Anup Patel [this message]
2025-07-02  5:13   ` [PATCH v7 03/24] RISC-V: Add defines for the SBI message proxy extension Anup Patel
2025-07-02 12:03   ` Andy Shevchenko
2025-07-02 12:03     ` Andy Shevchenko
2025-07-02 12:06   ` Andy Shevchenko
2025-07-02 12:06     ` Andy Shevchenko
2025-07-03  5:16     ` Anup Patel
2025-07-03  5:16       ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 04/24] mailbox: Add common header for RPMI messages sent via mailbox Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 05/24] mailbox: Allow controller specific mapping using fwnode Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02 12:32   ` Andy Shevchenko
2025-07-02 12:32     ` Andy Shevchenko
2025-07-02  5:13 ` [PATCH v7 06/24] byteorder: Add memcpy_to_le32() and memcpy_from_le32() Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02 11:30   ` Andy Shevchenko
2025-07-02 11:30     ` Andy Shevchenko
2025-07-04  8:16   ` Linus Walleij
2025-07-04  8:16     ` Linus Walleij
2025-07-02  5:13 ` [PATCH v7 07/24] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02 12:50   ` Andy Shevchenko
2025-07-02 12:50     ` Andy Shevchenko
2025-07-03  6:52     ` Anup Patel
2025-07-03  6:52       ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 08/24] dt-bindings: clock: Add RPMI clock service message proxy bindings Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 09/24] dt-bindings: clock: Add RPMI clock service controller bindings Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 10/24] clk: Add clock driver for the RISC-V RPMI clock service group Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02 13:08   ` Andy Shevchenko
2025-07-02 13:08     ` Andy Shevchenko
2025-07-04  4:15     ` Anup Patel
2025-07-04  4:15       ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 11/24] dt-bindings: Add RPMI system MSI message proxy bindings Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 12/24] dt-bindings: Add RPMI system MSI interrupt controller bindings Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 13/24] irqchip: Add driver for the RPMI system MSI service group Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 14/24] ACPI: property: Refactor acpi_fwnode_get_reference_args() Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02 10:07   ` Rafael J. Wysocki
2025-07-02 10:07     ` Rafael J. Wysocki
2025-07-02 14:45     ` Sunil V L
2025-07-02 14:45       ` Sunil V L
2025-07-02 17:01       ` Rafael J. Wysocki
2025-07-02 17:01         ` Rafael J. Wysocki
2025-07-02  5:13 ` [PATCH v7 15/24] ACPI: property: Add support for cells property Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02 10:20   ` Rafael J. Wysocki
2025-07-02 10:20     ` Rafael J. Wysocki
2025-07-02 11:37     ` Andy Shevchenko
2025-07-02 11:37       ` Andy Shevchenko
2025-07-02 11:39       ` Andy Shevchenko
2025-07-02 11:39         ` Andy Shevchenko
2025-07-02 12:39       ` Rafael J. Wysocki
2025-07-02 12:39         ` Rafael J. Wysocki
2025-07-02 12:56         ` Andy Shevchenko
2025-07-02 12:56           ` Andy Shevchenko
2025-07-02 13:16           ` Rafael J. Wysocki
2025-07-02 13:16             ` Rafael J. Wysocki
2025-07-02 15:06         ` Sunil V L
2025-07-02 15:06           ` Sunil V L
2025-07-02 16:56           ` Rafael J. Wysocki
2025-07-02 16:56             ` Rafael J. Wysocki
2025-07-03  9:31             ` Sunil V L
2025-07-03  9:31               ` Sunil V L
2025-07-02 11:44   ` Andy Shevchenko
2025-07-02 11:44     ` Andy Shevchenko
2025-07-02  5:13 ` [PATCH v7 16/24] ACPI: scan: Update honor list for RPMI System MSI Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02 10:21   ` Rafael J. Wysocki
2025-07-02 10:21     ` Rafael J. Wysocki
2025-07-02 11:45   ` Andy Shevchenko
2025-07-02 11:45     ` Andy Shevchenko
2025-07-02  5:13 ` [PATCH v7 17/24] ACPI: RISC-V: Create interrupt controller list in sorted order Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 18/24] ACPI: RISC-V: Add support to update gsi range Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 19/24] ACPI: RISC-V: Add RPMI System MSI to GSI mapping Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 20/24] irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode() Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 21/24] mailbox/riscv-sbi-mpxy: Add ACPI support Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02 12:28   ` Andy Shevchenko
2025-07-02 12:28     ` Andy Shevchenko
2025-07-03 10:54     ` Sunil V L
2025-07-03 10:54       ` Sunil V L
2025-07-03 13:54       ` Andy Shevchenko
2025-07-03 13:54         ` Andy Shevchenko
2025-07-03 14:26         ` Anup Patel
2025-07-03 14:26           ` Anup Patel
2025-07-03 14:32           ` Andy Shevchenko
2025-07-03 14:32             ` Andy Shevchenko
2025-07-02  5:13 ` [PATCH v7 22/24] irqchip/riscv-rpmi-sysmsi: " Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 23/24] RISC-V: Enable GPIO keyboard and event device in RV64 defconfig Anup Patel
2025-07-02  5:13   ` Anup Patel
2025-07-02  5:13 ` [PATCH v7 24/24] MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers Anup Patel
2025-07-02  5:13   ` Anup Patel

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