* Re: [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs
2025-07-08 6:07 [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs Xu Lu
@ 2025-07-08 8:32 ` Xu Lu
2025-07-15 10:03 ` Anup Patel
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Xu Lu @ 2025-07-08 8:32 UTC (permalink / raw)
To: palmer, alistair.francis, liwei1518, zhiwei_liu, apatel
Cc: qemu-riscv, qemu-devel
FYI, the discussion about whether vs insn fault or illegal insn fault
should be raised can be found from [1].
[1] https://lists.riscv.org/g/tech-privileged/message/2469
On Tue, Jul 8, 2025 at 2:07 PM Xu Lu <luxu.kernel@bytedance.com> wrote:
>
> When supervisor CSRs are accessed from VU-mode, a virtual instruction
> exception should be raised instead of an illegal instruction.
>
> Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking)
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8631be97c5..9bebfae3f0 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -5577,7 +5577,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>
> csr_priv = get_field(csrno, 0x300);
> if (!env->debugger && (effective_priv < csr_priv)) {
> - if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
> + if (csr_priv <= (PRV_S + 1) && env->virt_enabled) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> return RISCV_EXCP_ILLEGAL_INST;
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs
2025-07-08 6:07 [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs Xu Lu
2025-07-08 8:32 ` Xu Lu
@ 2025-07-15 10:03 ` Anup Patel
2025-07-21 7:40 ` Nutty Liu
2025-07-29 3:25 ` Alistair Francis
3 siblings, 0 replies; 5+ messages in thread
From: Anup Patel @ 2025-07-15 10:03 UTC (permalink / raw)
To: Xu Lu
Cc: palmer, alistair.francis, liwei1518, zhiwei_liu, qemu-riscv,
qemu-devel
On Tue, Jul 8, 2025 at 11:37 AM Xu Lu <luxu.kernel@bytedance.com> wrote:
>
> When supervisor CSRs are accessed from VU-mode, a virtual instruction
> exception should be raised instead of an illegal instruction.
>
> Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking)
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
LGTM.
Reviewed-by: Anup Patel <apatel@ventanamicro.com>
Regards,
Anup
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8631be97c5..9bebfae3f0 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -5577,7 +5577,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>
> csr_priv = get_field(csrno, 0x300);
> if (!env->debugger && (effective_priv < csr_priv)) {
> - if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
> + if (csr_priv <= (PRV_S + 1) && env->virt_enabled) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> return RISCV_EXCP_ILLEGAL_INST;
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs
2025-07-08 6:07 [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs Xu Lu
2025-07-08 8:32 ` Xu Lu
2025-07-15 10:03 ` Anup Patel
@ 2025-07-21 7:40 ` Nutty Liu
2025-07-29 3:25 ` Alistair Francis
3 siblings, 0 replies; 5+ messages in thread
From: Nutty Liu @ 2025-07-21 7:40 UTC (permalink / raw)
To: Xu Lu, palmer, alistair.francis, liwei1518, zhiwei_liu, apatel
Cc: qemu-riscv, qemu-devel
On 7/8/2025 2:07 PM, Xu Lu wrote:
> When supervisor CSRs are accessed from VU-mode, a virtual instruction
> exception should be raised instead of an illegal instruction.
>
> Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking)
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8631be97c5..9bebfae3f0 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -5577,7 +5577,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>
> csr_priv = get_field(csrno, 0x300);
> if (!env->debugger && (effective_priv < csr_priv)) {
> - if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
> + if (csr_priv <= (PRV_S + 1) && env->virt_enabled) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> return RISCV_EXCP_ILLEGAL_INST;
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Thanks,
Nutty
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs
2025-07-08 6:07 [PATCH] target/riscv: Fix exception type when VU accesses supervisor CSRs Xu Lu
` (2 preceding siblings ...)
2025-07-21 7:40 ` Nutty Liu
@ 2025-07-29 3:25 ` Alistair Francis
3 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2025-07-29 3:25 UTC (permalink / raw)
To: Xu Lu
Cc: palmer, alistair.francis, liwei1518, zhiwei_liu, apatel,
qemu-riscv, qemu-devel
On Wed, Jul 9, 2025 at 6:48 AM Xu Lu <luxu.kernel@bytedance.com> wrote:
>
> When supervisor CSRs are accessed from VU-mode, a virtual instruction
> exception should be raised instead of an illegal instruction.
>
> Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking)
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8631be97c5..9bebfae3f0 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -5577,7 +5577,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>
> csr_priv = get_field(csrno, 0x300);
> if (!env->debugger && (effective_priv < csr_priv)) {
> - if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
> + if (csr_priv <= (PRV_S + 1) && env->virt_enabled) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> return RISCV_EXCP_ILLEGAL_INST;
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread