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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Fam Zheng" <fam@euphon.net>
Subject: [PULL 12/17] esp.c: improve comment in esp_transfer_data()
Date: Tue, 15 Jul 2025 08:19:12 +0200	[thread overview]
Message-ID: <20250715061918.44971-13-philmd@linaro.org> (raw)
In-Reply-To: <20250715061918.44971-1-philmd@linaro.org>

From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

Whilst working on the previous patch, the existing comment was not enough to
document when the TI command codepath was being used. Update and improve the
comment accordingly.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250711204636.542964-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/scsi/esp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 9181c8810fb..62ba4061492 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -1029,8 +1029,9 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len)
         case CMD_TI | CMD_DMA:
         case CMD_TI:
             /*
-             * Bus service interrupt raised because of initial change to
-             * DATA phase
+             * If the final COMMAND phase data was transferred using a TI
+             * command, clear ESP_CMD to terminate the TI command and raise
+             * the completion interrupt
              */
             s->rregs[ESP_CMD] = 0;
             s->rregs[ESP_RINTR] |= INTR_BS;
-- 
2.49.0



  parent reply	other threads:[~2025-07-15  6:27 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-15  6:19 [PULL 00/17] MIPS & Co. patches for 2025-07-15 Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 01/17] target/mips: Add support for emulation of CRC32 instructions Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 02/17] target/mips: Extract gen_base_index_addr() helper Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 03/17] target/mips: Extract generic gen_lx() helper Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 04/17] target/mips: Convert Octeon LX instructions to decodetree Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 05/17] target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 06/17] tests/tcg/mips: Add tests for MIPS CRC32[c] instructions Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 07/17] roms: re-remove execute bit from hppa-firmware* Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 08/17] hw/mips: Restrict ITU to TCG Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 09/17] hw/intc/loongarch_extioi: Remove unnecessary 'qemu/typedefs.h' include Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 10/17] hw/microblaze: Add missing FDT dependency Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 11/17] esp.c: only raise IRQ in esp_transfer_data() for CMD_SEL, CMD_SELATN and CMD_TI commands Philippe Mathieu-Daudé
2025-07-15  6:19 ` Philippe Mathieu-Daudé [this message]
2025-07-15  6:19 ` [PULL 13/17] esp.h: remove separate ESPState typedef Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 14/17] esp.c: only call dma_memory_read function if transfer length is non-zero Philippe Mathieu-Daudé
2025-07-17 11:48   ` Philippe Mathieu-Daudé
2025-07-17 11:58     ` Peter Maydell
2025-07-17 12:37       ` Mark Cave-Ayland
2025-07-15  6:19 ` [PULL 15/17] esp.c: only call dma_memory_write " Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 16/17] esp.c: add asc_mode property to indicate the current ESP mode Philippe Mathieu-Daudé
2025-07-15  6:19 ` [PULL 17/17] esp.c: only allow ESP commands permitted in the current asc_mode Philippe Mathieu-Daudé
2025-07-15  6:50 ` [PULL 00/17] MIPS & Co. patches for 2025-07-15 Philippe Mathieu-Daudé
2025-07-16 12:40 ` Stefan Hajnoczi

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