From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Fam Zheng" <fam@euphon.net>
Subject: [PULL 17/17] esp.c: only allow ESP commands permitted in the current asc_mode
Date: Tue, 15 Jul 2025 08:19:17 +0200 [thread overview]
Message-ID: <20250715061918.44971-18-philmd@linaro.org> (raw)
In-Reply-To: <20250715061918.44971-1-philmd@linaro.org>
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
If an ESP command is issued in an incorrect mode then an illegal command
interrupt should be generated. Add a new esp_cmd_is_valid() function to
indicate whether the ESP command is valid for the current mode, and if not
then raise the illegal command interrupt.
This fixes WinNT MIPS which issues ICCS after a Chip Reset which is not
permitted, but will fail with an INACCESSIBLE_BOOT_DEVICE error unless an
interrupt is generated.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Fixes: 83428f7a97 ("esp.c: move write_response() non-DMA logic to esp_do_nodma()")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2464
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250711204636.542964-8-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/scsi/esp.h | 8 ++++++++
hw/scsi/esp.c | 37 +++++++++++++++++++++++++++++++++++++
hw/scsi/trace-events | 1 +
3 files changed, 46 insertions(+)
diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h
index 6327060c7c7..3526bad7464 100644
--- a/include/hw/scsi/esp.h
+++ b/include/hw/scsi/esp.h
@@ -111,6 +111,13 @@ struct SysBusESPState {
#define CMD_DMA 0x80
#define CMD_CMD 0x7f
+#define CMD_GRP_MASK 0x70
+
+#define CMD_GRP_MISC 0x00
+#define CMD_GRP_INIT 0x01
+#define CMD_GRP_TRGT 0x02
+#define CMD_GRP_DISC 0x04
+
#define CMD_NOP 0x00
#define CMD_FLUSH 0x01
#define CMD_RESET 0x02
@@ -145,6 +152,7 @@ struct SysBusESPState {
#define INTR_FC 0x08
#define INTR_BS 0x10
#define INTR_DC 0x20
+#define INTR_IL 0x40
#define INTR_RST 0x80
#define SEQ_0 0x0
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 4aa58f9e485..1d264c40e57 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -1129,6 +1129,38 @@ static void parent_esp_reset(ESPState *s, int irq, int level)
}
}
+static bool esp_cmd_is_valid(ESPState *s, uint8_t cmd)
+{
+ uint8_t cmd_group = (cmd & CMD_GRP_MASK) >> 4;
+
+ /* Always allow misc commands */
+ if (cmd_group == CMD_GRP_MISC) {
+ return true;
+ }
+
+ switch (s->asc_mode) {
+ case ESP_ASC_MODE_DIS:
+ /* Disconnected mode: only allow disconnected commands */
+ if (cmd_group == CMD_GRP_DISC) {
+ return true;
+ }
+ break;
+
+ case ESP_ASC_MODE_INI:
+ /* Initiator mode: allow initiator commands */
+ if (cmd_group == CMD_GRP_INIT) {
+ return true;
+ }
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ trace_esp_invalid_cmd(cmd, s->asc_mode);
+ return false;
+}
+
static void esp_run_cmd(ESPState *s)
{
uint8_t cmd = s->rregs[ESP_CMD];
@@ -1285,6 +1317,11 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
break;
case ESP_CMD:
s->rregs[saddr] = val;
+ if (!esp_cmd_is_valid(s, s->rregs[saddr])) {
+ s->rregs[ESP_RSTAT] |= INTR_IL;
+ esp_raise_irq(s);
+ break;
+ }
esp_run_cmd(s);
break;
case ESP_WBUSID ... ESP_WSYNO:
diff --git a/hw/scsi/trace-events b/hw/scsi/trace-events
index f0f2a98c2ee..6c2788e2026 100644
--- a/hw/scsi/trace-events
+++ b/hw/scsi/trace-events
@@ -198,6 +198,7 @@ esp_mem_writeb_cmd_ensel(uint32_t val) "Enable selection (0x%2.2x)"
esp_mem_writeb_cmd_dissel(uint32_t val) "Disable selection (0x%2.2x)"
esp_mem_writeb_cmd_ti(uint32_t val) "Transfer Information (0x%2.2x)"
esp_set_phase(const char *phase) "setting bus phase to %s"
+esp_invalid_cmd(uint8_t cmd, uint8_t asc_mode) "command 0x%x asc_mode 0x%x"
# esp-pci.c
esp_pci_error_invalid_dma_direction(void) "invalid DMA transfer direction"
--
2.49.0
next prev parent reply other threads:[~2025-07-15 6:27 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-15 6:19 [PULL 00/17] MIPS & Co. patches for 2025-07-15 Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 01/17] target/mips: Add support for emulation of CRC32 instructions Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 02/17] target/mips: Extract gen_base_index_addr() helper Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 03/17] target/mips: Extract generic gen_lx() helper Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 04/17] target/mips: Convert Octeon LX instructions to decodetree Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 05/17] target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 06/17] tests/tcg/mips: Add tests for MIPS CRC32[c] instructions Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 07/17] roms: re-remove execute bit from hppa-firmware* Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 08/17] hw/mips: Restrict ITU to TCG Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 09/17] hw/intc/loongarch_extioi: Remove unnecessary 'qemu/typedefs.h' include Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 10/17] hw/microblaze: Add missing FDT dependency Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 11/17] esp.c: only raise IRQ in esp_transfer_data() for CMD_SEL, CMD_SELATN and CMD_TI commands Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 12/17] esp.c: improve comment in esp_transfer_data() Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 13/17] esp.h: remove separate ESPState typedef Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 14/17] esp.c: only call dma_memory_read function if transfer length is non-zero Philippe Mathieu-Daudé
2025-07-17 11:48 ` Philippe Mathieu-Daudé
2025-07-17 11:58 ` Peter Maydell
2025-07-17 12:37 ` Mark Cave-Ayland
2025-07-15 6:19 ` [PULL 15/17] esp.c: only call dma_memory_write " Philippe Mathieu-Daudé
2025-07-15 6:19 ` [PULL 16/17] esp.c: add asc_mode property to indicate the current ESP mode Philippe Mathieu-Daudé
2025-07-15 6:19 ` Philippe Mathieu-Daudé [this message]
2025-07-15 6:50 ` [PULL 00/17] MIPS & Co. patches for 2025-07-15 Philippe Mathieu-Daudé
2025-07-16 12:40 ` Stefan Hajnoczi
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