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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <shiju.jose@huawei.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
	<dave.jiang@intel.com>, <alison.schofield@intel.com>,
	<dave@stgolabs.net>, <vishal.l.verma@intel.com>,
	<ira.weiny@intel.com>, <tanxiaofei@huawei.com>,
	<prime.zeng@hisilicon.com>, <linuxarm@huawei.com>
Subject: Re: [PATCH 1/4] cxl/events: Update Common Event Record to CXL spec rev 3.2
Date: Wed, 16 Jul 2025 13:53:33 +0100	[thread overview]
Message-ID: <20250716135333.00001670@huawei.com> (raw)
In-Reply-To: <20250716104945.2002-2-shiju.jose@huawei.com>

On Wed, 16 Jul 2025 11:49:42 +0100
<shiju.jose@huawei.com> wrote:

> From: Shiju Jose <shiju.jose@huawei.com>
> 
> CXL spec 3.2 section 8.2.10.2.1 Table 8-55, Common Event Record format
> defined new fields LD-ID and Head ID.
> 
> LD-ID: ID of logical device from where the event originated, which is
> valid only if LD-ID valid flag is set to 1.
> CXL spec 3.2 Section 2.4 describes, a Type 3 Multi-Logical Device (MLD)
> can partition its resources into up to 16 isolated Logical Devices.
> Each Logical Device is identified by a Logical Device Identifier (LD-ID)
> in CXL.mem and CXL.io protocols. LD-ID is a 16-bit Logical Device
> identifier applicable for CXL.io and CXL.mem requests and responses.
> CXL.mem supports only the lower 4 bits of LD-ID and therefore can support
> up to 16 unique LD-ID values over the link. Requests and responses
> forwarded over an MLD Port are tagged with LD-ID.
> 
> Head ID: ID of the device head, from where the event originated, which is
> valid only if head valid flag is set to 1.
> 
> Add updates for the above spec changes in the CXL events record and CXL
> common trace event implementation.
> 
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>

  reply	other threads:[~2025-07-16 12:53 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-16 10:49 [PATCH 0/4] cxl/events: Update to rev 3.2, improvements and add trace memory sparing event record shiju.jose
2025-07-16 10:49 ` [PATCH 1/4] cxl/events: Update Common Event Record to CXL spec rev 3.2 shiju.jose
2025-07-16 12:53   ` Jonathan Cameron [this message]
2025-07-16 10:49 ` [PATCH 2/4] cxl/events: Add extra validity checks for corrected memory error count in General Media Event Record shiju.jose
2025-07-16 13:04   ` Jonathan Cameron
2025-07-16 21:40   ` Dave Jiang
2025-07-17  3:32   ` kernel test robot
2025-07-16 10:49 ` [PATCH 3/4] cxl/events: Add extra validity checks for CVME count in DRAM " shiju.jose
2025-07-16 13:07   ` Jonathan Cameron
2025-07-16 21:53   ` Dave Jiang
2025-07-17  5:16   ` kernel test robot
2025-07-16 10:49 ` [PATCH 4/4] cxl/events: Trace Memory Sparing " shiju.jose
2025-07-16 13:16   ` Jonathan Cameron
2025-07-16 15:07     ` Shiju Jose
2025-07-16 22:23   ` Dave Jiang

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