From: Rob Herring <robh@kernel.org>
To: Louis Chauvet <louis.chauvet@bootlin.com>
Cc: Jyri Sarha <jyri.sarha@iki.fi>,
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Sam Ravnborg <sam@ravnborg.org>, Benoit Parrot <bparrot@ti.com>,
Lee Jones <lee@kernel.org>, Nishanth Menon <nm@ti.com>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>,
thomas.petazzoni@bootlin.com, Jyri Sarha <jsarha@ti.com>,
Tomi Valkeinen <tomi.valkeinen@ti.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: display: ti,am65x-dss: Add clk property for data edge synchronization
Date: Wed, 30 Jul 2025 18:56:53 -0500 [thread overview]
Message-ID: <20250730235653.GA1914482-robh@kernel.org> (raw)
In-Reply-To: <20250730-fix-edge-handling-v1-1-1bdfb3fe7922@bootlin.com>
On Wed, Jul 30, 2025 at 07:02:44PM +0200, Louis Chauvet wrote:
> The dt-bindings for the display, specifically ti,am65x-dss, need to
> include a clock property for data edge synchronization. The current
> implementation does not correctly apply the data edge sampling property.
>
> To address this, synchronization of writes to two different registers is
> required: one in the TIDSS IP (which is already described in the tidss
> node) and one is in the Memory Mapped Control Register Modules (added by
> the previous commit).
>
> As the Memory Mapped Control Register Modules is located in a different
> IP, we need to use a phandle to write values in its registers.
You can always just lookup the target node by compatible. Then you don't
need a DT update to solve your problem.
>
> Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display SubSystem")
> Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
>
> ---
>
> Cc: stable@vger.kernel.org
> ---
> Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 361e9cae6896c1f4d7fa1ec47a6e3a73bca2b102..b9a373b569170332f671416eb7bbc0c83f7b5ea6 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -133,6 +133,12 @@ properties:
> and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
> interface to work.
>
> + ti,clk-ctrl:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to syscon device node mapping CFG0_CLK_CTRL registers.
> + This property is needed for proper data sampling edge.
> +
> max-memory-bandwidth:
> $ref: /schemas/types.yaml#/definitions/uint32
> description:
>
> --
> 2.50.1
>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Louis Chauvet <louis.chauvet@bootlin.com>
Cc: Jyri Sarha <jyri.sarha@iki.fi>,
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Sam Ravnborg <sam@ravnborg.org>, Benoit Parrot <bparrot@ti.com>,
Lee Jones <lee@kernel.org>, Nishanth Menon <nm@ti.com>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>,
thomas.petazzoni@bootlin.com, Jyri Sarha <jsarha@ti.com>,
Tomi Valkeinen <tomi.valkeinen@ti.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: display: ti, am65x-dss: Add clk property for data edge synchronization
Date: Wed, 30 Jul 2025 18:56:53 -0500 [thread overview]
Message-ID: <20250730235653.GA1914482-robh@kernel.org> (raw)
In-Reply-To: <20250730-fix-edge-handling-v1-1-1bdfb3fe7922@bootlin.com>
On Wed, Jul 30, 2025 at 07:02:44PM +0200, Louis Chauvet wrote:
> The dt-bindings for the display, specifically ti,am65x-dss, need to
> include a clock property for data edge synchronization. The current
> implementation does not correctly apply the data edge sampling property.
>
> To address this, synchronization of writes to two different registers is
> required: one in the TIDSS IP (which is already described in the tidss
> node) and one is in the Memory Mapped Control Register Modules (added by
> the previous commit).
>
> As the Memory Mapped Control Register Modules is located in a different
> IP, we need to use a phandle to write values in its registers.
You can always just lookup the target node by compatible. Then you don't
need a DT update to solve your problem.
>
> Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display SubSystem")
> Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
>
> ---
>
> Cc: stable@vger.kernel.org
> ---
> Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 361e9cae6896c1f4d7fa1ec47a6e3a73bca2b102..b9a373b569170332f671416eb7bbc0c83f7b5ea6 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -133,6 +133,12 @@ properties:
> and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
> interface to work.
>
> + ti,clk-ctrl:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to syscon device node mapping CFG0_CLK_CTRL registers.
> + This property is needed for proper data sampling edge.
> +
> max-memory-bandwidth:
> $ref: /schemas/types.yaml#/definitions/uint32
> description:
>
> --
> 2.50.1
>
next prev parent reply other threads:[~2025-07-31 0:00 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-30 17:02 [PATCH 0/4] drm/tidss: Fixes data edge sampling Louis Chauvet
2025-07-30 17:02 ` [PATCH 1/4] dt-bindings: display: ti,am65x-dss: Add clk property for data edge synchronization Louis Chauvet
2025-07-30 23:56 ` Rob Herring [this message]
2025-07-30 23:56 ` [PATCH 1/4] dt-bindings: display: ti, am65x-dss: " Rob Herring
2025-07-31 9:50 ` [PATCH 1/4] dt-bindings: display: ti,am65x-dss: " Louis Chauvet
2025-07-31 9:50 ` [PATCH 1/4] dt-bindings: display: ti, am65x-dss: " Louis Chauvet
2025-07-30 17:02 ` [PATCH 2/4] dt-bindings: mfd: syscon: Add ti,am625-dss-clk-ctrl Louis Chauvet
2025-08-04 8:04 ` Krzysztof Kozlowski
2025-07-30 17:02 ` [PATCH 3/4] arm64: dts: ti: k3-am62-main: Add tidss clk-ctrl property Louis Chauvet
2025-07-31 0:17 ` Rob Herring
2025-07-31 9:50 ` Louis Chauvet
2025-08-05 6:44 ` Krzysztof Kozlowski
2025-08-11 9:56 ` Louis Chauvet
2025-07-30 17:02 ` [PATCH 4/4] drm/tidss: Fix sampling edge configuration Louis Chauvet
2025-08-04 8:06 ` Krzysztof Kozlowski
2025-08-08 13:46 ` devarsh
2025-08-08 16:26 ` Swamil Jain
2025-08-11 9:56 ` Louis Chauvet
2025-08-12 18:02 ` Swamil Jain
2025-08-12 18:10 ` Swamil Jain
2025-08-07 13:21 ` [PATCH 0/4] drm/tidss: Fixes data edge sampling Tomi Valkeinen
2025-08-08 13:24 ` devarsh
2025-08-11 7:56 ` Tomi Valkeinen
2025-08-11 9:56 ` Louis Chauvet
2025-10-10 7:42 ` Swamil Jain
2025-10-27 17:53 ` Swamil Jain
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