[openeuler:OLK-6.6 2630/2630] drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:4039:39: sparse: sparse: incorrect type in assignment (different base types)

[openeuler:OLK-6.6 2630/2630] drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:4039:39: sparse: sparse: incorrect type in assignment (different base types)

[kernel test robot]

tree:   https://gitee.com/openeuler/kernel.git OLK-6.6
head:   8fa27fba5fd9db50ef3d03358c9abd371dcbdd99
commit: 587296e12d7d64c971a182ca1d28de8cdbe29ca9 [2630/2630] iommu/arm-smmu-v3: Add mpam helpers to query and set state
config: arm64-randconfig-r111-20250803 (https://download.01.org/0day-ci/archive/20250803/202508030926.Js3SWM6z-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce: (https://download.01.org/0day-ci/archive/20250803/202508030926.Js3SWM6z-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508030926.Js3SWM6z-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:4039:39: sparse: sparse: incorrect type in assignment (different base types) @@     expected restricted __le64 @@     got unsigned long long @@
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:4039:39: sparse:     expected restricted __le64
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:4039:39: sparse:     got unsigned long long
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:4040:39: sparse: sparse: incorrect type in assignment (different base types) @@     expected restricted __le64 @@     got unsigned long long @@
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:4040:39: sparse:     expected restricted __le64
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:4040:39: sparse:     got unsigned long long
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c: note: in included file (through arch/arm64/include/asm/atomic.h, include/linux/atomic.h, include/asm-generic/bitops/atomic.h, ...):
   arch/arm64/include/asm/cmpxchg.h:168:1: sparse: sparse: cast truncates bits from constant value (ffffffff80000000 becomes 0)
   arch/arm64/include/asm/cmpxchg.h:168:1: sparse: sparse: cast truncates bits from constant value (ffffffff80000000 becomes 0)

vim +4039 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

  4000	
  4001	static int arm_smmu_group_set_mpam(struct iommu_group *group, u16 partid,
  4002					   u8 pmg)
  4003	{
  4004		int i;
  4005		u32 sid;
  4006		unsigned long flags;
  4007		struct arm_smmu_ste *step;
  4008		struct iommu_domain *domain;
  4009		struct arm_smmu_device *smmu;
  4010		struct arm_smmu_master *master;
  4011		struct arm_smmu_cmdq_batch cmds;
  4012		struct arm_smmu_domain *smmu_domain;
  4013		struct arm_smmu_cmdq_ent cmd = {
  4014			.opcode	= CMDQ_OP_CFGI_STE,
  4015			.cfgi	= {
  4016				.leaf	= true,
  4017			},
  4018		};
  4019		struct arm_smmu_master_domain *master_domain;
  4020	
  4021		domain = iommu_get_domain_for_group(group);
  4022		smmu_domain = to_smmu_domain(domain);
  4023		if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_MPAM))
  4024			return -EIO;
  4025		smmu = smmu_domain->smmu;
  4026	
  4027		arm_smmu_cmdq_batch_init(smmu, &cmds);
  4028	
  4029		spin_lock_irqsave(&smmu_domain->devices_lock, flags);
  4030		list_for_each_entry(master_domain, &smmu_domain->devices,
  4031				    devices_elm) {
  4032			master = master_domain->master;
  4033	
  4034			for (i = 0; i < master->num_streams; i++) {
  4035				sid = master->streams[i].id;
  4036				step = arm_smmu_get_step_for_sid(smmu, sid);
  4037	
  4038				/* These need locking if the VMSPtr is ever used */
> 4039				step->data[4] = FIELD_PREP(STRTAB_STE_4_PARTID, partid);
  4040				step->data[5] = FIELD_PREP(STRTAB_STE_5_PMG, pmg);
  4041	
  4042				cmd.cfgi.sid = sid;
  4043				arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);
  4044			}
  4045	
  4046			master->partid = partid;
  4047			master->pmg = pmg;
  4048		}
  4049		spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
  4050	
  4051		arm_smmu_cmdq_batch_submit(smmu, &cmds);
  4052	
  4053		return 0;
  4054	}
  4055	

-- 
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