[PATCH 27/38] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address

[PATCH 27/38] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address

[AngeloGioacchino Del Regno]

The PCIe and USB TPHYs are under the soc bus, which provides MMIO,
and all nodes under that must use the bus, otherwise those would
clearly be out of place.

Add ranges to both the tphy(s) and assign the address to the main
node to silence a dtbs_check warning, and fix the children to
use the MMIO range of t-phy.

Fixes: ("f693e6ba55ae arm64: dts: mediatek: mt7988: Add t-phy for ssusb1")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 28 +++++++++++------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 560ec86dbec0..cc0d3e3f4374 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -629,20 +629,20 @@ pcie_intc1: interrupt-controller {
 		tphy: t-phy@11c50000 {
 			compatible = "mediatek,mt7986-tphy",
 				     "mediatek,generic-tphy-v2";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11c50000 0x1000>;
 			status = "disabled";
 
-			tphyu2port0: usb-phy@11c50000 {
-				reg = <0 0x11c50000 0 0x700>;
+			tphyu2port0: usb-phy@0 {
+				reg = <0 0x700>;
 				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 			};
 
-			tphyu3port0: usb-phy@11c50700 {
-				reg = <0 0x11c50700 0 0x900>;
+			tphyu3port0: usb-phy@700 {
+				reg = <0 0x700 0 0x900>;
 				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
 				clock-names = "ref";
 				#phy-cells = <1>;
@@ -659,20 +659,20 @@ topmisc: system-controller@11d10084 {
 		xsphy: xs-phy@11e10000 {
 			compatible = "mediatek,mt7988-xsphy",
 				     "mediatek,xsphy";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11e10000 0x3900>;
 			status = "disabled";
 
-			xphyu2port0: usb-phy@11e10000 {
-				reg = <0 0x11e10000 0 0x400>;
+			xphyu2port0: usb-phy@0 {
+				reg = <0 0x400>;
 				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 			};
 
-			xphyu3port0: usb-phy@11e13000 {
-				reg = <0 0x11e13400 0 0x500>;
+			xphyu3port0: usb-phy@3400 {
+				reg = <0x3400 0x500>;
 				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
 				clock-names = "ref";
 				#phy-cells = <1>;
-- 
2.50.1

[PATCH 27/38] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address

[AngeloGioacchino Del Regno]

The PCIe and USB TPHYs are under the soc bus, which provides MMIO,
and all nodes under that must use the bus, otherwise those would
clearly be out of place.

Add ranges to both the tphy(s) and assign the address to the main
node to silence a dtbs_check warning, and fix the children to
use the MMIO range of t-phy.

Fixes: ("f693e6ba55ae arm64: dts: mediatek: mt7988: Add t-phy for ssusb1")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 28 +++++++++++------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 560ec86dbec0..cc0d3e3f4374 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -629,20 +629,20 @@ pcie_intc1: interrupt-controller {
 		tphy: t-phy@11c50000 {
 			compatible = "mediatek,mt7986-tphy",
 				     "mediatek,generic-tphy-v2";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11c50000 0x1000>;
 			status = "disabled";
 
-			tphyu2port0: usb-phy@11c50000 {
-				reg = <0 0x11c50000 0 0x700>;
+			tphyu2port0: usb-phy@0 {
+				reg = <0 0x700>;
 				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 			};
 
-			tphyu3port0: usb-phy@11c50700 {
-				reg = <0 0x11c50700 0 0x900>;
+			tphyu3port0: usb-phy@700 {
+				reg = <0 0x700 0 0x900>;
 				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
 				clock-names = "ref";
 				#phy-cells = <1>;
@@ -659,20 +659,20 @@ topmisc: system-controller@11d10084 {
 		xsphy: xs-phy@11e10000 {
 			compatible = "mediatek,mt7988-xsphy",
 				     "mediatek,xsphy";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11e10000 0x3900>;
 			status = "disabled";
 
-			xphyu2port0: usb-phy@11e10000 {
-				reg = <0 0x11e10000 0 0x400>;
+			xphyu2port0: usb-phy@0 {
+				reg = <0 0x400>;
 				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 			};
 
-			xphyu3port0: usb-phy@11e13000 {
-				reg = <0 0x11e13400 0 0x500>;
+			xphyu3port0: usb-phy@3400 {
+				reg = <0x3400 0x500>;
 				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
 				clock-names = "ref";
 				#phy-cells = <1>;
-- 
2.50.1

[PATCH 27/38] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address

[AngeloGioacchino Del Regno]

The PCIe and USB TPHYs are under the soc bus, which provides MMIO,
and all nodes under that must use the bus, otherwise those would
clearly be out of place.

Add ranges to both the tphy(s) and assign the address to the main
node to silence a dtbs_check warning, and fix the children to
use the MMIO range of t-phy.

Fixes: ("f693e6ba55ae arm64: dts: mediatek: mt7988: Add t-phy for ssusb1")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 28 +++++++++++------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 560ec86dbec0..cc0d3e3f4374 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -629,20 +629,20 @@ pcie_intc1: interrupt-controller {
 		tphy: t-phy@11c50000 {
 			compatible = "mediatek,mt7986-tphy",
 				     "mediatek,generic-tphy-v2";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11c50000 0x1000>;
 			status = "disabled";
 
-			tphyu2port0: usb-phy@11c50000 {
-				reg = <0 0x11c50000 0 0x700>;
+			tphyu2port0: usb-phy@0 {
+				reg = <0 0x700>;
 				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 			};
 
-			tphyu3port0: usb-phy@11c50700 {
-				reg = <0 0x11c50700 0 0x900>;
+			tphyu3port0: usb-phy@700 {
+				reg = <0 0x700 0 0x900>;
 				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
 				clock-names = "ref";
 				#phy-cells = <1>;
@@ -659,20 +659,20 @@ topmisc: system-controller@11d10084 {
 		xsphy: xs-phy@11e10000 {
 			compatible = "mediatek,mt7988-xsphy",
 				     "mediatek,xsphy";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0x11e10000 0x3900>;
 			status = "disabled";
 
-			xphyu2port0: usb-phy@11e10000 {
-				reg = <0 0x11e10000 0 0x400>;
+			xphyu2port0: usb-phy@0 {
+				reg = <0 0x400>;
 				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 			};
 
-			xphyu3port0: usb-phy@11e13000 {
-				reg = <0 0x11e13400 0 0x500>;
+			xphyu3port0: usb-phy@3400 {
+				reg = <0x3400 0x500>;
 				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
 				clock-names = "ref";
 				#phy-cells = <1>;
-- 
2.50.1


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Re: [PATCH 27/38] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address

[Frank Wunderlich]

Am 24. Juli 2025 10:39:03 MESZ schrieb AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>:
>The PCIe and USB TPHYs are under the soc bus, which provides MMIO,
>and all nodes under that must use the bus, otherwise those would
>clearly be out of place.
>
>Add ranges to both the tphy(s) and assign the address to the main
>node to silence a dtbs_check warning, and fix the children to
>use the MMIO range of t-phy.
>
>Fixes: ("f693e6ba55ae arm64: dts: mediatek: mt7988: Add t-phy for ssusb1")
>Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>---
> arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 28 +++++++++++------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>index 560ec86dbec0..cc0d3e3f4374 100644
>--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>@@ -629,20 +629,20 @@ pcie_intc1: interrupt-controller {
> 		tphy: t-phy@11c50000 {
> 			compatible = "mediatek,mt7986-tphy",
> 				     "mediatek,generic-tphy-v2";
>-			#address-cells = <2>;
>-			#size-cells = <2>;
>-			ranges;
>+			#address-cells = <1>;
>+			#size-cells = <1>;
>+			ranges = <0 0 0x11c50000 0x1000>;
> 			status = "disabled";
> 
>-			tphyu2port0: usb-phy@11c50000 {
>-				reg = <0 0x11c50000 0 0x700>;
>+			tphyu2port0: usb-phy@0 {
>+				reg = <0 0x700>;
> 				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
> 				clock-names = "ref";
> 				#phy-cells = <1>;
> 			};
> 
>-			tphyu3port0: usb-phy@11c50700 {
>-				reg = <0 0x11c50700 0 0x900>;
>+			tphyu3port0: usb-phy@700 {
>+				reg = <0 0x700 0 0x900>;

This one looks wrong to me

I guess it should be 

reg = <0x700 0x900>;

> 				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
> 				clock-names = "ref";
> 				#phy-cells = <1>;
>@@ -659,20 +659,20 @@ topmisc: system-controller@11d10084 {
> 		xsphy: xs-phy@11e10000 {
> 			compatible = "mediatek,mt7988-xsphy",
> 				     "mediatek,xsphy";
>-			#address-cells = <2>;
>-			#size-cells = <2>;
>-			ranges;
>+			#address-cells = <1>;
>+			#size-cells = <1>;
>+			ranges = <0 0 0x11e10000 0x3900>;
> 			status = "disabled";
> 
>-			xphyu2port0: usb-phy@11e10000 {
>-				reg = <0 0x11e10000 0 0x400>;
>+			xphyu2port0: usb-phy@0 {
>+				reg = <0 0x400>;
> 				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
> 				clock-names = "ref";
> 				#phy-cells = <1>;
> 			};
> 
>-			xphyu3port0: usb-phy@11e13000 {
>-				reg = <0 0x11e13400 0 0x500>;
>+			xphyu3port0: usb-phy@3400 {
>+				reg = <0x3400 0x500>;
> 				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
> 				clock-names = "ref";
> 				#phy-cells = <1>;

Hi Angelo,

thanks for taking case of many of current binding errors (only wondering about this one as i had checked it before sending upstream).
regards Frank

Re: [PATCH 27/38] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address

[Frank Wunderlich]

Am 24. Juli 2025 10:39:03 MESZ schrieb AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>:
>The PCIe and USB TPHYs are under the soc bus, which provides MMIO,
>and all nodes under that must use the bus, otherwise those would
>clearly be out of place.
>
>Add ranges to both the tphy(s) and assign the address to the main
>node to silence a dtbs_check warning, and fix the children to
>use the MMIO range of t-phy.
>
>Fixes: ("f693e6ba55ae arm64: dts: mediatek: mt7988: Add t-phy for ssusb1")
>Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>---
> arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 28 +++++++++++------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
>diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>index 560ec86dbec0..cc0d3e3f4374 100644
>--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
>@@ -629,20 +629,20 @@ pcie_intc1: interrupt-controller {
> 		tphy: t-phy@11c50000 {
> 			compatible = "mediatek,mt7986-tphy",
> 				     "mediatek,generic-tphy-v2";
>-			#address-cells = <2>;
>-			#size-cells = <2>;
>-			ranges;
>+			#address-cells = <1>;
>+			#size-cells = <1>;
>+			ranges = <0 0 0x11c50000 0x1000>;
> 			status = "disabled";
> 
>-			tphyu2port0: usb-phy@11c50000 {
>-				reg = <0 0x11c50000 0 0x700>;
>+			tphyu2port0: usb-phy@0 {
>+				reg = <0 0x700>;
> 				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
> 				clock-names = "ref";
> 				#phy-cells = <1>;
> 			};
> 
>-			tphyu3port0: usb-phy@11c50700 {
>-				reg = <0 0x11c50700 0 0x900>;
>+			tphyu3port0: usb-phy@700 {
>+				reg = <0 0x700 0 0x900>;

This one looks wrong to me

I guess it should be 

reg = <0x700 0x900>;

> 				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
> 				clock-names = "ref";
> 				#phy-cells = <1>;
>@@ -659,20 +659,20 @@ topmisc: system-controller@11d10084 {
> 		xsphy: xs-phy@11e10000 {
> 			compatible = "mediatek,mt7988-xsphy",
> 				     "mediatek,xsphy";
>-			#address-cells = <2>;
>-			#size-cells = <2>;
>-			ranges;
>+			#address-cells = <1>;
>+			#size-cells = <1>;
>+			ranges = <0 0 0x11e10000 0x3900>;
> 			status = "disabled";
> 
>-			xphyu2port0: usb-phy@11e10000 {
>-				reg = <0 0x11e10000 0 0x400>;
>+			xphyu2port0: usb-phy@0 {
>+				reg = <0 0x400>;
> 				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
> 				clock-names = "ref";
> 				#phy-cells = <1>;
> 			};
> 
>-			xphyu3port0: usb-phy@11e13000 {
>-				reg = <0 0x11e13400 0 0x500>;
>+			xphyu3port0: usb-phy@3400 {
>+				reg = <0x3400 0x500>;
> 				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
> 				clock-names = "ref";
> 				#phy-cells = <1>;

Hi Angelo,

thanks for taking case of many of current binding errors (only wondering about this one as i had checked it before sending upstream).
regards Frank

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Re: [PATCH 27/38] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address

[kernel test robot]

:::::: 
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
:::::: 

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250724083914.61351-28-angelogioacchino.delregno@collabora.com>
References: <20250724083914.61351-28-angelogioacchino.delregno@collabora.com>
TO: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
TO: linux-mediatek@lists.infradead.org
TO: robh@kernel.org
CC: herbert@gondor.apana.org.au
CC: davem@davemloft.net
CC: krzk+dt@kernel.org
CC: conor+dt@kernel.org
CC: chunkuang.hu@kernel.org
CC: p.zabel@pengutronix.de
CC: airlied@gmail.com
CC: simona@ffwll.ch
CC: maarten.lankhorst@linux.intel.com
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CC: angelogioacchino.delregno@collabora.com
CC: chunfeng.yun@mediatek.com
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CC: linus.walleij@linaro.org
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CC: mathieu.poirier@linaro.org
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CC: atenart@kernel.org
CC: jitao.shi@mediatek.com

Hi AngeloGioacchino,

kernel test robot noticed the following build warnings:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linusw-pinctrl/devel linusw-pinctrl/for-next broonie-regulator/for-next v6.16]
[cannot apply to linus/master next-20250801]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/AngeloGioacchino-Del-Regno/dt-bindings-display-mediatek-dpi-Allow-specifying-resets/20250724-164429
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20250724083914.61351-28-angelogioacchino.delregno%40collabora.com
patch subject: [PATCH 27/38] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address
:::::: branch date: 10 days ago
:::::: commit date: 10 days ago
config: arm64-randconfig-051-20250728 (https://download.01.org/0day-ci/archive/20250803/202508030717.YkeR4MZ3-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 8.5.0
dtschema version: 2025.6.2.dev4+g8f79ddd
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250803/202508030717.YkeR4MZ3-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202508030717.YkeR4MZ3-lkp@intel.com/

dtcheck warnings: (new ones prefixed by >>)
>> arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtb: t-phy@11c50000 (mediatek,mt7986-tphy): usb-phy@700:reg: [[0, 1792], [0, 2304]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
--
>> arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dtb: t-phy@11c50000 (mediatek,mt7986-tphy): usb-phy@700:reg: [[0, 1792], [0, 2304]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#

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Re: [PATCH 27/38] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address

[kernel test robot]

:::::: 
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
:::::: 

BCC: lkp@intel.com
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Hi AngeloGioacchino,

kernel test robot noticed the following build warnings:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linusw-pinctrl/devel linusw-pinctrl/for-next broonie-regulator/for-next v6.16]
[cannot apply to linus/master next-20250801]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/AngeloGioacchino-Del-Regno/dt-bindings-display-mediatek-dpi-Allow-specifying-resets/20250724-164429
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20250724083914.61351-28-angelogioacchino.delregno%40collabora.com
patch subject: [PATCH 27/38] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address
:::::: branch date: 11 days ago
:::::: commit date: 11 days ago
config: arm64-randconfig-051-20250728 (https://download.01.org/0day-ci/archive/20250804/202508040745.ZlihAsOD-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 8.5.0
dtschema version: 2025.6.2.dev4+g8f79ddd
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250804/202508040745.ZlihAsOD-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202508040745.ZlihAsOD-lkp@intel.com/

dtcheck warnings: (new ones prefixed by >>)
>> arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtb: t-phy@11c50000 (mediatek,mt7986-tphy): usb-phy@700:reg: [[0, 1792], [0, 2304]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
--
>> arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dtb: t-phy@11c50000 (mediatek,mt7986-tphy): usb-phy@700:reg: [[0, 1792], [0, 2304]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki