From: Imre Deak <imre.deak@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <intel-xe@lists.freedesktop.org>
Subject: [PATCH 17/19] dmc/i915/tc: Report pin assignment NONE in TBT-alt mode
Date: Tue, 5 Aug 2025 10:36:58 +0300 [thread overview]
Message-ID: <20250805073700.642107-18-imre.deak@intel.com> (raw)
In-Reply-To: <20250805073700.642107-1-imre.deak@intel.com>
The pin assignment is only relevant in case the PHY is owned by the
display, that is in legacy and DP-alt mode. In TBT-alt mode the PHY is
owned by the TBT FW/driver and so the pin assignment/configuration is
managed by those components. A follow-up change will cache the pin
assignment value in all the TypeC modes - querying this by calling
get_pin_assignment() - prepare for that here, by reporting pin
assignment NONE in the TBT-alt mode.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index cd4f0179b8cc4..d874217529951 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -287,6 +287,9 @@ get_pin_assignment(struct intel_tc_port *tc)
u32 mask;
u32 val;
+ if (tc->mode == TC_PORT_TBT_ALT)
+ return INTEL_TC_PIN_ASSIGNMENT_NONE;
+
if (DISPLAY_VER(display) >= 20) {
reg = TCSS_DDI_STATUS(tc_port);
mask = TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK;
--
2.49.1
next prev parent reply other threads:[~2025-08-05 7:37 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-05 7:36 [PATCH 00/19] drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Imre Deak
2025-08-05 7:36 ` [PATCH 01/19] drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sink Imre Deak
2025-08-07 7:06 ` Kahola, Mika
2025-08-07 10:59 ` Luca Coelho
2025-08-07 11:38 ` Imre Deak
2025-08-07 12:19 ` Jani Nikula
2025-08-07 12:32 ` Imre Deak
2025-08-07 12:50 ` Imre Deak
2025-08-07 13:05 ` Jani Nikula
2025-08-07 13:24 ` Imre Deak
2025-08-07 14:10 ` Luca Coelho
2025-08-05 7:36 ` [PATCH 02/19] drm/i915/icl+/tc: Cache the max lane count value Imre Deak
2025-08-05 9:33 ` [PATCH v2 " Imre Deak
2025-08-07 8:07 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 03/19] drm/i915/lnl+/tc: Fix max lane count HW readout Imre Deak
2025-08-05 9:33 ` [PATCH v2 " Imre Deak
2025-08-07 8:36 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 04/19] drm/i915/lnl+/tc: Use the cached max lane count value Imre Deak
2025-08-07 8:49 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 05/19] drm/i915/icl+/tc: Convert AUX powered WARN to a debug message Imre Deak
2025-08-07 12:29 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 06/19] drm/i915/tc: Use the cached max lane count value Imre Deak
2025-08-06 12:02 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 07/19] drm/i915/tc: Move getting the power domain before reading DFLEX registers Imre Deak
2025-08-06 12:56 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 08/19] drm/i915/tc: Move asserting the power state after reading TCSS_DDI_STATUS Imre Deak
2025-08-06 13:22 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 09/19] drm/i915/tc: Add an enum for the TypeC pin assignment Imre Deak
2025-08-07 12:39 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 10/19] drm/i915/tc: Pass pin assignment value around using the pin assignment enum Imre Deak
2025-08-07 12:56 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 11/19] drm/i915/tc: Handle pin assignment NONE on all platforms Imre Deak
2025-08-07 12:57 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 12/19] drm/i915/tc: Validate the pin assignment " Imre Deak
2025-08-07 13:08 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 13/19] drm/i915/tc: Unify the way to get " Imre Deak
2025-08-08 6:44 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 14/19] drm/i915/tc: Unify the way to get the max lane count value on MTL+ Imre Deak
2025-08-08 7:32 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 15/19] drm/i915/tc: Handle non-TC encoders when getting the pin assignment Imre Deak
2025-08-08 7:45 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 16/19] drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpers Imre Deak
2025-08-08 8:25 ` Kahola, Mika
2025-08-05 7:36 ` Imre Deak [this message]
2025-08-08 8:26 ` [PATCH 17/19] dmc/i915/tc: Report pin assignment NONE in TBT-alt mode Kahola, Mika
2025-08-05 7:36 ` [PATCH 18/19] drm/i915/tc: Cache the pin assignment value Imre Deak
2025-08-08 8:27 ` Kahola, Mika
2025-08-05 7:37 ` [PATCH 19/19] drm/i915/tc: Debug print the pin assignment and max lane count Imre Deak
2025-08-08 8:28 ` Kahola, Mika
2025-08-05 7:46 ` ✗ CI.checkpatch: warning for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Patchwork
2025-08-05 7:47 ` ✓ CI.KUnit: success " Patchwork
2025-08-05 8:02 ` ✗ CI.checksparse: warning " Patchwork
2025-08-05 8:49 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-08-05 9:10 ` ✗ i915.CI.BAT: " Patchwork
2025-08-05 10:08 ` ✓ Xe.CI.Full: success " Patchwork
2025-08-05 10:47 ` ✓ i915.CI.BAT: success for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling (rev3) Patchwork
2025-08-05 11:41 ` ✗ CI.checkpatch: warning " Patchwork
2025-08-05 11:42 ` ✓ CI.KUnit: success " Patchwork
2025-08-05 11:57 ` ✗ CI.checksparse: warning " Patchwork
2025-08-05 12:51 ` ✗ i915.CI.Full: failure " Patchwork
2025-08-13 12:43 ` Imre Deak
2025-08-05 13:02 ` ✓ Xe.CI.BAT: success " Patchwork
2025-08-05 15:31 ` ✓ Xe.CI.Full: " Patchwork
2025-08-06 11:44 ` [PATCH 00/19] drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Luca Coelho
2025-08-06 11:54 ` Imre Deak
2025-08-06 12:54 ` Luca Coelho
2025-08-06 13:12 ` Imre Deak
2025-08-06 13:16 ` Luca Coelho
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