[PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Rick Wertenbroek]

Both PHYs can use an alternate reference differential clock, add the clocks
to the DT bindings

Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
---
 .../devicetree/bindings/phy/rockchip,pcie3-phy.yaml   | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
index d7de8b527c5c..b747930b18f1 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
@@ -20,11 +20,11 @@ properties:
 
   clocks:
     minItems: 1
-    maxItems: 3
+    maxItems: 5
 
   clock-names:
     minItems: 1
-    maxItems: 3
+    maxItems: 5
 
   data-lanes:
     description: which lanes (by position) should be mapped to which
@@ -82,10 +82,15 @@ allOf:
     then:
       properties:
         clocks:
-          maxItems: 1
+          minItems: 1
+          maxItems: 5
         clock-names:
           items:
             - const: pclk
+            - const: phy0_ref_alt_p
+            - const: phy0_ref_alt_m
+            - const: phy1_ref_alt_p
+            - const: phy1_ref_alt_m
     else:
       properties:
         clocks:
-- 
2.25.1

[PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Rick Wertenbroek]

Both PHYs can use an alternate reference differential clock, add the clocks
to the DT bindings

Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
---
 .../devicetree/bindings/phy/rockchip,pcie3-phy.yaml   | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
index d7de8b527c5c..b747930b18f1 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
@@ -20,11 +20,11 @@ properties:
 
   clocks:
     minItems: 1
-    maxItems: 3
+    maxItems: 5
 
   clock-names:
     minItems: 1
-    maxItems: 3
+    maxItems: 5
 
   data-lanes:
     description: which lanes (by position) should be mapped to which
@@ -82,10 +82,15 @@ allOf:
     then:
       properties:
         clocks:
-          maxItems: 1
+          minItems: 1
+          maxItems: 5
         clock-names:
           items:
             - const: pclk
+            - const: phy0_ref_alt_p
+            - const: phy0_ref_alt_m
+            - const: phy1_ref_alt_p
+            - const: phy1_ref_alt_m
     else:
       properties:
         clocks:
-- 
2.25.1


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[PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Rick Wertenbroek]

Both PHYs can use an alternate reference differential clock, add the clocks
to the DT bindings

Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
---
 .../devicetree/bindings/phy/rockchip,pcie3-phy.yaml   | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
index d7de8b527c5c..b747930b18f1 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
@@ -20,11 +20,11 @@ properties:
 
   clocks:
     minItems: 1
-    maxItems: 3
+    maxItems: 5
 
   clock-names:
     minItems: 1
-    maxItems: 3
+    maxItems: 5
 
   data-lanes:
     description: which lanes (by position) should be mapped to which
@@ -82,10 +82,15 @@ allOf:
     then:
       properties:
         clocks:
-          maxItems: 1
+          minItems: 1
+          maxItems: 5
         clock-names:
           items:
             - const: pclk
+            - const: phy0_ref_alt_p
+            - const: phy0_ref_alt_m
+            - const: phy1_ref_alt_p
+            - const: phy1_ref_alt_m
     else:
       properties:
         clocks:
-- 
2.25.1


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Re: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Krzysztof Kozlowski]

On Wed, Aug 06, 2025 at 03:38:21PM +0200, Rick Wertenbroek wrote:
> Both PHYs can use an alternate reference differential clock, add the clocks

I do not see any changes in rockchip,rk3588-pcie3-phy, so your "both" is
either incorrect or ambiguous.

...

> to the DT bindings
> 
  
>    data-lanes:
>      description: which lanes (by position) should be mapped to which
> @@ -82,10 +82,15 @@ allOf:
>      then:
>        properties:
>          clocks:
> -          maxItems: 1
> +          minItems: 1
> +          maxItems: 5
>          clock-names:
>            items:
>              - const: pclk
> +            - const: phy0_ref_alt_p
> +            - const: phy0_ref_alt_m
> +            - const: phy1_ref_alt_p
> +            - const: phy1_ref_alt_m

These are different clock inputs?

>      else:
>        properties:
>          clocks:

You need to update the example as well.

> -- 
> 2.25.1
> 

Re: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Krzysztof Kozlowski]

On Wed, Aug 06, 2025 at 03:38:21PM +0200, Rick Wertenbroek wrote:
> Both PHYs can use an alternate reference differential clock, add the clocks

I do not see any changes in rockchip,rk3588-pcie3-phy, so your "both" is
either incorrect or ambiguous.

...

> to the DT bindings
> 
  
>    data-lanes:
>      description: which lanes (by position) should be mapped to which
> @@ -82,10 +82,15 @@ allOf:
>      then:
>        properties:
>          clocks:
> -          maxItems: 1
> +          minItems: 1
> +          maxItems: 5
>          clock-names:
>            items:
>              - const: pclk
> +            - const: phy0_ref_alt_p
> +            - const: phy0_ref_alt_m
> +            - const: phy1_ref_alt_p
> +            - const: phy1_ref_alt_m

These are different clock inputs?

>      else:
>        properties:
>          clocks:

You need to update the example as well.

> -- 
> 2.25.1
> 

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Re: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Krzysztof Kozlowski]

On Wed, Aug 06, 2025 at 03:38:21PM +0200, Rick Wertenbroek wrote:
> Both PHYs can use an alternate reference differential clock, add the clocks

I do not see any changes in rockchip,rk3588-pcie3-phy, so your "both" is
either incorrect or ambiguous.

...

> to the DT bindings
> 
  
>    data-lanes:
>      description: which lanes (by position) should be mapped to which
> @@ -82,10 +82,15 @@ allOf:
>      then:
>        properties:
>          clocks:
> -          maxItems: 1
> +          minItems: 1
> +          maxItems: 5
>          clock-names:
>            items:
>              - const: pclk
> +            - const: phy0_ref_alt_p
> +            - const: phy0_ref_alt_m
> +            - const: phy1_ref_alt_p
> +            - const: phy1_ref_alt_m

These are different clock inputs?

>      else:
>        properties:
>          clocks:

You need to update the example as well.

> -- 
> 2.25.1
> 

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Re: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Krzysztof Kozlowski]

On 07/08/2025 09:42, Krzysztof Kozlowski wrote:
> On Wed, Aug 06, 2025 at 03:38:21PM +0200, Rick Wertenbroek wrote:
>> Both PHYs can use an alternate reference differential clock, add the clocks
> 
> I do not see any changes in rockchip,rk3588-pcie3-phy, so your "both" is

I meant 3568, the other one.

> either incorrect or ambiguous.
> 
> ...
> 
>> to the DT bindings
>>

Best regards,
Krzysztof

Re: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Krzysztof Kozlowski]

On 07/08/2025 09:42, Krzysztof Kozlowski wrote:
> On Wed, Aug 06, 2025 at 03:38:21PM +0200, Rick Wertenbroek wrote:
>> Both PHYs can use an alternate reference differential clock, add the clocks
> 
> I do not see any changes in rockchip,rk3588-pcie3-phy, so your "both" is

I meant 3568, the other one.

> either incorrect or ambiguous.
> 
> ...
> 
>> to the DT bindings
>>

Best regards,
Krzysztof

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Re: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Krzysztof Kozlowski]

On 07/08/2025 09:42, Krzysztof Kozlowski wrote:
> On Wed, Aug 06, 2025 at 03:38:21PM +0200, Rick Wertenbroek wrote:
>> Both PHYs can use an alternate reference differential clock, add the clocks
> 
> I do not see any changes in rockchip,rk3588-pcie3-phy, so your "both" is

I meant 3568, the other one.

> either incorrect or ambiguous.
> 
> ...
> 
>> to the DT bindings
>>

Best regards,
Krzysztof

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Re: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Rick Wertenbroek]

On Thu, Aug 7, 2025 at 9:44 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 07/08/2025 09:42, Krzysztof Kozlowski wrote:
> > On Wed, Aug 06, 2025 at 03:38:21PM +0200, Rick Wertenbroek wrote:
> >> Both PHYs can use an alternate reference differential clock, add the clocks
> >
> > I do not see any changes in rockchip,rk3588-pcie3-phy, so your "both" is
>
> I meant 3568, the other one.
>

By "both" I meant both PHYs of the RK3588 as the rk3588-pcie-phy is
actually a dual PHY (PHY0 and PHY1 which both can use independent
clocks).

The RK3588 PHY is a dual PHY with two independent PCIe 3.0 x2
interfaces (that can be combined into an x4 or used independently).
The RK3568 PHY is a single PHY with one PCIe 3.0 x2 interface.

The RK3568 already has the bindings for the extra differential clock
for its PHY, but the RK3588 did not, so I added them.

I should maybe rephrase this to make it clearer it applies only to the
RK3588 and that by both PHYs I mean RK3588 PHY0 and PHY1

> > either incorrect or ambiguous.
> >
> > ...
> >
> >> to the DT bindings
> >>
>
> Best regards,
> Krzysztof

Re: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Rick Wertenbroek]

On Thu, Aug 7, 2025 at 9:44 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 07/08/2025 09:42, Krzysztof Kozlowski wrote:
> > On Wed, Aug 06, 2025 at 03:38:21PM +0200, Rick Wertenbroek wrote:
> >> Both PHYs can use an alternate reference differential clock, add the clocks
> >
> > I do not see any changes in rockchip,rk3588-pcie3-phy, so your "both" is
>
> I meant 3568, the other one.
>

By "both" I meant both PHYs of the RK3588 as the rk3588-pcie-phy is
actually a dual PHY (PHY0 and PHY1 which both can use independent
clocks).

The RK3588 PHY is a dual PHY with two independent PCIe 3.0 x2
interfaces (that can be combined into an x4 or used independently).
The RK3568 PHY is a single PHY with one PCIe 3.0 x2 interface.

The RK3568 already has the bindings for the extra differential clock
for its PHY, but the RK3588 did not, so I added them.

I should maybe rephrase this to make it clearer it applies only to the
RK3588 and that by both PHYs I mean RK3588 PHY0 and PHY1

> > either incorrect or ambiguous.
> >
> > ...
> >
> >> to the DT bindings
> >>
>
> Best regards,
> Krzysztof

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Re: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[Rick Wertenbroek]

On Thu, Aug 7, 2025 at 9:44 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 07/08/2025 09:42, Krzysztof Kozlowski wrote:
> > On Wed, Aug 06, 2025 at 03:38:21PM +0200, Rick Wertenbroek wrote:
> >> Both PHYs can use an alternate reference differential clock, add the clocks
> >
> > I do not see any changes in rockchip,rk3588-pcie3-phy, so your "both" is
>
> I meant 3568, the other one.
>

By "both" I meant both PHYs of the RK3588 as the rk3588-pcie-phy is
actually a dual PHY (PHY0 and PHY1 which both can use independent
clocks).

The RK3588 PHY is a dual PHY with two independent PCIe 3.0 x2
interfaces (that can be combined into an x4 or used independently).
The RK3568 PHY is a single PHY with one PCIe 3.0 x2 interface.

The RK3568 already has the bindings for the extra differential clock
for its PHY, but the RK3588 did not, so I added them.

I should maybe rephrase this to make it clearer it applies only to the
RK3588 and that by both PHYs I mean RK3588 PHY0 and PHY1

> > either incorrect or ambiguous.
> >
> > ...
> >
> >> to the DT bindings
> >>
>
> Best regards,
> Krzysztof

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Re: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks

[kernel test robot]

:::::: 
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
:::::: 

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250806133824.525871-2-rick.wertenbroek@gmail.com>
References: <20250806133824.525871-2-rick.wertenbroek@gmail.com>
TO: Rick Wertenbroek <rick.wertenbroek@gmail.com>
CC: rick.wertenbroek@heig-vd.ch
CC: dlemoal@kernel.org
CC: alberto.dassatti@heig-vd.ch
CC: Rick Wertenbroek <rick.wertenbroek@gmail.com>
CC: Vinod Koul <vkoul@kernel.org>
CC: Kishon Vijay Abraham I <kishon@kernel.org>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk@kernel.org>
CC: Conor Dooley <conor+dt@kernel.org>
CC: Heiko Stuebner <heiko@sntech.de>
CC: linux-phy@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-rockchip@lists.infradead.org
CC: linux-kernel@vger.kernel.org

Hi Rick,

kernel test robot noticed the following build warnings:

[auto build test WARNING on robh/for-next]
[also build test WARNING on rockchip/for-next linus/master v6.16 next-20250807]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Rick-Wertenbroek/dt-bindings-phy-rockchip-pcie3-phy-add-optional-differential-phy-clocks/20250806-214044
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20250806133824.525871-2-rick.wertenbroek%40gmail.com
patch subject: [PATCH v2 1/3] dt-bindings: phy: rockchip,pcie3-phy: add optional differential phy clocks
:::::: branch date: 27 hours ago
:::::: commit date: 27 hours ago
config: arm64-randconfig-051-20250807 (https://download.01.org/0day-ci/archive/20250808/202508080012.o5DCSPmD-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 10.5.0
dtschema version: 2025.6.2.dev4+g8f79ddd
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250808/202508080012.o5DCSPmD-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202508080012.o5DCSPmD-lkp@intel.com/

dtcheck warnings: (new ones prefixed by >>)
>> arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
   arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts:1393.7-1401.4: Warning (graph_child_address): /usb@fc000000/port: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
>> arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
   arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts:626.7-634.4: Warning (graph_child_address): /usb@fc000000/port: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
>> arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
   arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts:1110.7-1117.4: Warning (avoid_unnecessary_addr_size): /usb@fc000000/port: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property
   arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts:1125.7-1132.4: Warning (avoid_unnecessary_addr_size): /usb@fc400000/port: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property
   arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts:1110.7-1117.4: Warning (graph_child_address): /usb@fc000000/port: graph node has single child node 'endpoint', #address-cells/#size-cells are not necessary
   arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts:1125.7-1132.4: Warning (graph_child_address): /usb@fc400000/port: graph node has single child node 'endpoint', #address-cells/#size-cells are not necessary
>> arch/arm64/boot/dts/rockchip/rk3588-jaguar.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
   arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts:1186.7-1194.4: Warning (graph_child_address): /usb@fc000000/port: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
>> arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-wifi.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
   arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtb: pcie-ep@fe150000 (rockchip,rk3588-pcie-ep): Unevaluated properties are not allowed ('vpcie3v3-supply' was unexpected)
   	from schema $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
>> arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
--
>> arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-haikou-video-demo.dtb: phy@fee80000 (rockchip,rk3588-pcie3-phy): clock-names: ['pclk'] is too short
   	from schema $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki