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From: Anup Patel <apatel@ventanamicro.com>
To: Sunil V L <sunilvl@ventanamicro.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Alexandre Ghiti <alex@ghiti.fr>, Len Brown <lenb@kernel.org>,
	Atish Patra <atish.patra@linux.dev>,
	Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 1/2] ACPI: RISC-V: Fix FFH_CPPC_CSR error handling
Date: Fri, 15 Aug 2025 21:44:05 +0530	[thread overview]
Message-ID: <20250815161406.76370-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20250815161406.76370-1-apatel@ventanamicro.com>

The cppc_ffh_csr_read() and cppc_ffh_csr_write() returns Linux error
code in "data->ret.error" so cpc_read_ffh() and cpc_write_ffh() must
not use sbi_err_map_linux_errno() for FFH_CPPC_CSR.

Fixes: 30f3ffbee86b ("ACPI: RISC-V: Add CPPC driver")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 drivers/acpi/riscv/cppc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c
index 440cf9fb91aa..42c1a9052470 100644
--- a/drivers/acpi/riscv/cppc.c
+++ b/drivers/acpi/riscv/cppc.c
@@ -119,7 +119,7 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
 
 		*val = data.ret.value;
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
 	}
 
 	return -EINVAL;
@@ -148,7 +148,7 @@ int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
 
 		smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
 	}
 
 	return -EINVAL;
-- 
2.43.0


WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Sunil V L <sunilvl@ventanamicro.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Alexandre Ghiti <alex@ghiti.fr>, Len Brown <lenb@kernel.org>,
	Atish Patra <atish.patra@linux.dev>,
	Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 1/2] ACPI: RISC-V: Fix FFH_CPPC_CSR error handling
Date: Fri, 15 Aug 2025 21:44:05 +0530	[thread overview]
Message-ID: <20250815161406.76370-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20250815161406.76370-1-apatel@ventanamicro.com>

The cppc_ffh_csr_read() and cppc_ffh_csr_write() returns Linux error
code in "data->ret.error" so cpc_read_ffh() and cpc_write_ffh() must
not use sbi_err_map_linux_errno() for FFH_CPPC_CSR.

Fixes: 30f3ffbee86b ("ACPI: RISC-V: Add CPPC driver")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 drivers/acpi/riscv/cppc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c
index 440cf9fb91aa..42c1a9052470 100644
--- a/drivers/acpi/riscv/cppc.c
+++ b/drivers/acpi/riscv/cppc.c
@@ -119,7 +119,7 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
 
 		*val = data.ret.value;
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
 	}
 
 	return -EINVAL;
@@ -148,7 +148,7 @@ int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
 
 		smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
 	}
 
 	return -EINVAL;
-- 
2.43.0


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  reply	other threads:[~2025-08-15 16:14 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-15 16:14 [PATCH 0/2] Common csr_read_num() and csr_write_num() for RISC-V Anup Patel
2025-08-15 16:14 ` Anup Patel
2025-08-15 16:14 ` Anup Patel [this message]
2025-08-15 16:14   ` [PATCH 1/2] ACPI: RISC-V: Fix FFH_CPPC_CSR error handling Anup Patel
2025-08-15 19:36   ` Andrew Jones
2025-08-15 19:36     ` Andrew Jones
2025-08-16  7:30   ` Troy Mitchell
2025-08-16  7:30     ` Troy Mitchell
2025-08-18  4:07   ` Sunil V L
2025-08-18  4:07     ` Sunil V L
2025-08-15 16:14 ` [PATCH 2/2] RISC-V: Add common csr_read_num() and csr_write_num() functions Anup Patel
2025-08-15 16:14   ` Anup Patel
2025-08-15 20:02   ` Andrew Jones
2025-08-15 20:02     ` Andrew Jones
2025-08-16  8:30     ` Anup Patel
2025-08-16  8:30       ` Anup Patel
2025-08-16  4:24   ` Vivian Wang
2025-08-16  4:24     ` Vivian Wang
2025-08-16  5:59     ` Vivian Wang
2025-08-16  5:59       ` Vivian Wang
2025-08-16  8:42     ` Anup Patel
2025-08-16  8:42       ` Anup Patel
2025-08-16 11:26       ` Vivian Wang
2025-08-16 11:26         ` Vivian Wang
2025-08-18  4:09   ` Sunil V L
2025-08-18  4:09     ` Sunil V L

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