From: Jamin Lin via <qemu-arm@nongnu.org>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Cédric Le Goater" <clg@kaod.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<nabihestefan@google.com>, <wuhaotsh@google.com>,
<titusr@google.com>
Subject: [PATCH v1 07/11] tests/functional/test_arm_aspeed_ast2600: Add PCIe test via root port and e1000e
Date: Tue, 19 Aug 2025 17:01:28 +0800 [thread overview]
Message-ID: <20250819090141.3949136-8-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250819090141.3949136-1-jamin_lin@aspeedtech.com>
Add a functional test that exercises the AST2600 PCIe RC_H by creating a
root port and an e1000e endpoint behind it. The AST2600/ASPEED driver
treats root bus 0x80 specially: only two device addresses are usable on
the root bus, addr 0 (ASPEED host bridge) and addr 8. To attach endpoints
without code changes, the test places a QEMU PCIe root port at 0x80:08.0
and hangs e1000e behind it so the endpoint enumerates on bus 0x81.
The test appends:
-device pcie-root-port,id=root_port0,slot=1,addr=8,bus=pcie.0
-device e1000e,netdev=net0,bus=root_port0
-netdev user,id=net0
It then verifies enumeration with lspci:
0001:80:00.0 Host bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
0001:80:08.0 PCI bridge: Red Hat, Inc. QEMU PCIe Root port
0001:81:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
Connection
This is a temporary solution that allows attaching multiple PCIe
devices while the ASPEED drivers does not support placing endpoints directly
on bus numbers 0x80.
Reference:
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/drivers/pci/controller/pcie-aspeed.c#L309
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
tests/functional/test_arm_aspeed_ast2600.py | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/tests/functional/test_arm_aspeed_ast2600.py b/tests/functional/test_arm_aspeed_ast2600.py
index fdae4c939d..9ffcef513d 100755
--- a/tests/functional/test_arm_aspeed_ast2600.py
+++ b/tests/functional/test_arm_aspeed_ast2600.py
@@ -110,6 +110,10 @@ def test_arm_ast2600_evb_sdk(self):
'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test')
self.vm.add_args('-device',
'ds1338,bus=aspeed.i2c.bus.5,address=0x32')
+ self.vm.add_args('-device',
+ 'pcie-root-port,id=root_port0,slot=1,addr=8,bus=pcie.0')
+ self.vm.add_args('-device', 'e1000e,netdev=net0,bus=root_port0')
+ self.vm.add_args('-netdev', 'user,id=net0')
self.do_test_arm_aspeed_sdk_start(
self.scratch_file("ast2600-default", "image-bmc"))
@@ -136,5 +140,15 @@ def test_arm_ast2600_evb_sdk(self):
exec_command_and_wait_for_pattern(self,
'/sbin/hwclock -f /dev/rtc1', year)
+ exec_command_and_wait_for_pattern(self,
+ 'lspci -s 0001:80:00.0',
+ '0001:80:00.0 Host bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge')
+ exec_command_and_wait_for_pattern(self,
+ 'lspci -s 0001:80:08.0',
+ '0001:80:08.0 PCI bridge: Red Hat, Inc. QEMU PCIe Root port')
+ exec_command_and_wait_for_pattern(self,
+ 'lspci -s 0001:81:00.0',
+ '0001:81:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection')
+
if __name__ == '__main__':
AspeedTest.main()
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Cédric Le Goater" <clg@kaod.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<nabihestefan@google.com>, <wuhaotsh@google.com>,
<titusr@google.com>
Subject: [PATCH v1 07/11] tests/functional/test_arm_aspeed_ast2600: Add PCIe test via root port and e1000e
Date: Tue, 19 Aug 2025 17:01:28 +0800 [thread overview]
Message-ID: <20250819090141.3949136-8-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250819090141.3949136-1-jamin_lin@aspeedtech.com>
Add a functional test that exercises the AST2600 PCIe RC_H by creating a
root port and an e1000e endpoint behind it. The AST2600/ASPEED driver
treats root bus 0x80 specially: only two device addresses are usable on
the root bus, addr 0 (ASPEED host bridge) and addr 8. To attach endpoints
without code changes, the test places a QEMU PCIe root port at 0x80:08.0
and hangs e1000e behind it so the endpoint enumerates on bus 0x81.
The test appends:
-device pcie-root-port,id=root_port0,slot=1,addr=8,bus=pcie.0
-device e1000e,netdev=net0,bus=root_port0
-netdev user,id=net0
It then verifies enumeration with lspci:
0001:80:00.0 Host bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
0001:80:08.0 PCI bridge: Red Hat, Inc. QEMU PCIe Root port
0001:81:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
Connection
This is a temporary solution that allows attaching multiple PCIe
devices while the ASPEED drivers does not support placing endpoints directly
on bus numbers 0x80.
Reference:
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/drivers/pci/controller/pcie-aspeed.c#L309
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
tests/functional/test_arm_aspeed_ast2600.py | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/tests/functional/test_arm_aspeed_ast2600.py b/tests/functional/test_arm_aspeed_ast2600.py
index fdae4c939d..9ffcef513d 100755
--- a/tests/functional/test_arm_aspeed_ast2600.py
+++ b/tests/functional/test_arm_aspeed_ast2600.py
@@ -110,6 +110,10 @@ def test_arm_ast2600_evb_sdk(self):
'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test')
self.vm.add_args('-device',
'ds1338,bus=aspeed.i2c.bus.5,address=0x32')
+ self.vm.add_args('-device',
+ 'pcie-root-port,id=root_port0,slot=1,addr=8,bus=pcie.0')
+ self.vm.add_args('-device', 'e1000e,netdev=net0,bus=root_port0')
+ self.vm.add_args('-netdev', 'user,id=net0')
self.do_test_arm_aspeed_sdk_start(
self.scratch_file("ast2600-default", "image-bmc"))
@@ -136,5 +140,15 @@ def test_arm_ast2600_evb_sdk(self):
exec_command_and_wait_for_pattern(self,
'/sbin/hwclock -f /dev/rtc1', year)
+ exec_command_and_wait_for_pattern(self,
+ 'lspci -s 0001:80:00.0',
+ '0001:80:00.0 Host bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge')
+ exec_command_and_wait_for_pattern(self,
+ 'lspci -s 0001:80:08.0',
+ '0001:80:08.0 PCI bridge: Red Hat, Inc. QEMU PCIe Root port')
+ exec_command_and_wait_for_pattern(self,
+ 'lspci -s 0001:81:00.0',
+ '0001:81:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection')
+
if __name__ == '__main__':
AspeedTest.main()
--
2.43.0
next prev parent reply other threads:[~2025-08-19 9:02 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-19 9:01 [PATCH v1 00/11] Support PCIe RC to AST2600 and AST2700 Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-08-19 9:01 ` [PATCH v1 01/11] hw/pci/pci_ids Add PCI vendor ID for ASPEED Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-09-02 14:02 ` [SPAM] " Cédric Le Goater
2025-08-19 9:01 ` [PATCH v1 02/11] hw/pci-host/aspeed: Add AST2600 PCIe PHY model Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-08-19 9:01 ` [PATCH v1 03/11] hw/pci-host/aspeed: Add AST2600 PCIe config and host bridge Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-08-19 9:01 ` [PATCH v1 04/11] hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-08-19 9:01 ` [PATCH v1 05/11] hw/arm/aspeed: Wire up PCIe devices in SoC model Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-08-19 9:01 ` [PATCH v1 06/11] hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only) Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via [this message]
2025-08-19 9:01 ` [PATCH v1 07/11] tests/functional/test_arm_aspeed_ast2600: Add PCIe test via root port and e1000e Jamin Lin via
2025-08-19 9:01 ` [PATCH v1 08/11] hw/pci-host/aspeed: Add AST2700 PCIe PHY Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-08-19 9:01 ` [PATCH v1 09/11] hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocks Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-08-19 9:01 ` [PATCH v1 10/11] hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700 Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-08-19 9:01 ` [PATCH v1 11/11] tests/functional: Add PCIe presence test " Jamin Lin via
2025-08-19 9:01 ` Jamin Lin via
2025-09-02 14:00 ` [SPAM] [PATCH v1 00/11] Support PCIe RC to AST2600 and AST2700 Cédric Le Goater
2025-09-03 2:15 ` Jamin Lin
2025-09-04 3:15 ` Jamin Lin
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